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data sheet 100123b september 2000 BT868/bt869 flicker-free video encoder with ultrascale tm technology the BT868/869 is specifically designed for video systems requiring the generation of high-quality flicker-free composite and y/c (s-video) signals from various ycrcb or rgb digital streams. the BT868/869 accepts any input format from 640 x 480 to 800 x 600 resolution. the BT868/869 uses conexant?s ultrascale? technology to provide the most advanced vertical and horizontal scaling necessary for the display of non-interlaced data on interlaced devices such as the tv. the ultrascale? technology converts the lines of input pixel data to the appropriate number of output lines for producing a full-screen, high-quality image. the BT868/869 performs 5-line vertical filtering, which includes poly phase interpolation scaling for overscan compensation and flicker filtering. horizontal scaling for overscan compensation is achieved by altering the encoder clock frequency. this approach preserves all of the high frequency components of the input signals, which are essential for the highest quality display of text intensive images such as web pages on tvs. the amount of flicker filtering and overscan compensation is programmable. worldwide video standards are supported, including ntsc-m (n. america, taiwan, japan), pal-b,d,g,h,i (europe, asia), pal-m (brazil), pal-n (uruguay, paraguay), and pal-nc (argentina). BT868 and bt869 are functionally identical, with the exception that bt869 can output macrovision level 7.0 anticopy algorithm. functional block diagram input flicker fifo video xtal pll dac daca dacb internal comp fsadjust vref bias vbias p[23:0] xtalin xtalout clko clki sic sid altaddr hsync* vsync* blank* field reset* sleep slave pal mux encoder color space dacc timing serial clock demux interface filter/scaler conversion reference generation osc gen distinguishing features digital rgb or ycrcb non-interlaced input to interlaced or non-interlaced analog tv output modes: ycrcb modes: ? 16-bit 4:2:2 multiplexed 8-bit ? 24-bit 4:4:4 multiplexed 12-bit ? 24-bit 4:4:4 non-multiplexed 24-bit rgb modes: ? 15/16 bit 5:6:5 rgb multiplexed 8-bit ? 24-bit 8:8:8 rgb mulitplexed 12-bit ? 24-bit 8:8:8 rgb non-multiplexed 24-bit digital rgb non-interlaced input to analog rgb noninterlaced (vga/svga) output modes: ? 15/16 bit 5:6:5 rgb multiplexed 8-bit ? 24-bit 8:8:8 rgb mulitplexed 12-bit ? 24-bit 8:8:8 rgb non-multiplexed 24-bit support for ntsc/pal outputs in the following modes: ? interlaced and non-interlaced outputs ? s-video output (simultaneous with composite ntsc or pal outputs) ? component yuv analog output mode 5-line vertical filtering scaling for overscan compensation and flicker filtering ccir601 compatible input mode luma and chroma comb filtering 3 x 10-bit dacs 6 mhz luma bandwidth macrovision 7.0 copy protection 80-pin pqfp package 3.3 v operation with 5 v tolerant ios 2-line serial programming interface power-down modes master/slave video timing operation tv connected register flag automatic configuration applications desktop/portable pcs with tv-out living-room pcs internet pc/tvs internet appliances
100123b conexant ? 2000, conexant systems, inc. all rights reserved. information in this document is provided in connection with conexant systems, inc. (?conexant?) products. these materials are provided by conexant as a service to its customers and may be used for informational purposes only. conexant assumes no responsibility for errors or omissions in these materials. conexant may make changes to specifications and product descriptions at any time, without notice. conexant makes no commitment to update the information and shall have no responsibility whatsoever fo r conflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as provided in conexant?s terms and conditions of sale for such products, conexant assumes no liability whatsoever. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of conexant products including liability or warranties relating to fitness for a particular purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellectual property right. conexant further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. conexant shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. conexant products are not intended for use in medical, lifesaving or life sustaining applications. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting from such improper use or sale. the following are trademarks of conexant systems, inc.: conexant?, the conexant c symbol, and ?what?s next in communications technologies??. product names or services listed in this publication are for identification purposes only, and may be trademark s of third parties. third-party brands and names are the property of their respective owners. for additional disclaimer information, please consult conexant?s legal information posted at www.conexant.com , which is incorporated by reference. reader response: conexant strives to produce quality documentation and welcomes your feedback. please send comments and suggestions to tech.pubs@conexant.com . for technical questions, contact your local conexant sales office or field applications engineer. ordering information model number package ambient temperature range reduced features BT868krf 80-pin pqfp 0 c to +70 c no macrovision feature bt869krf 80-pin pqfp 0 c to +70 c ?
100123b conexant iii table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 gui controller programmability and frequency requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 9 1.3.3 timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3.4 device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.3.5 auto configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.3.6 clocking and timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.7 master and slave modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.3.8 input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.9 pixel input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.10 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.11 ycrcb inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.3.12 rgb inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.13 video amplitude scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.14 input pixel horizontal sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.15 input pixel vertical sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.3.16 input pixel blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.3.17 overscan compensation and flicker filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.3.18 vga compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.19 analog horizontal sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.20 analog vertical sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.21 analog video blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.22 video standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.23 subcarrier generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.3.24 burst generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.3.25 chrominance disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.3.26 digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.3.27 subcarrier phasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
table of contents BT868/bt869 flicker-free video encoder with ultrascale tm technology iv conexant 100123b 1.3.28 noninterlaced operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 1.3.29 closed captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.3.30 internal color bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.3.31 macrovision encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.3.32 outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.3.33 output connection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.3.34 output filtering and sinx/x compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.3.35 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.3.36 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 2.0 internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 essential registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 writing addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 reading information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3.0 pc board considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 power and ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 device decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.2 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 comp decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.4 vref decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.5 vbias decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4 signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.2 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5.1 electrostatic discharge and latchup considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5.2 clock and subcarrier stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5.3 filtering radio frequency modulator connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.6 BT868/bt869 evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.7 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.7.1 data transfer on the serial interface bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 4.0 parametric information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 appendix a. scaling and i/o timing register calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 appendix b. approved crystal vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1
BT868/bt869 list of figures flicker-free video encoder with ultrascale tm technology 100123b conexant vii list of figures figure 1-1. pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 figure 1-2. flicker filter control diagram ? external use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 figure 1-3. encoder core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 figure 1-4. decimation filter at fs=27 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 figure 1-5. interlaced 525-line (ntsc) video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 figure 1-6. interlaced 525-line (pal-m) video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 figure 1-7. interlaced 625-line (pal ? b, d, g, h, i, nc) video timing (fields 1 ? 4) . . . . . . . . . . . . . . . 1-24 figure 1-8. interlaced 625-line (pal ? b, d, g, h, i, nc) video timing (fields 5 ? 8) . . . . . . . . . . . . . . . 1-25 figure 1-9. interlaced 625-line (pal ? n) video timing (fields 1 ? 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 figure 1-10. interlaced 625-line (pal ? n) video timing (fields 5 ? 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 figure 1-11. noninterlaced 262-line (ntsc) video timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 figure 1-12. noninterlaced 262-line (pal ? m) video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 figure 1-13. noninterlaced 312-line (pal ? b, d, g, h, i, n, nc) video timing . . . . . . . . . . . . . . . . . . . 1-29 figure 1-14. three-stage chroma filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 figure 1-15. luminance upsampling filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 figure 3-1. power plane illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-2. connection diagram for output filters and other key passive components . . . . . . . . . . . . 3-3 figure 3-3. complete BT868/bt869 recommended layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 figure 3-4. BT868/bt869 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 figure 3-5. sid/sic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 figure 4-1. interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 figure 4-2. master mode with flicker filter interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 figure 4-3. slave mode with flicker filter interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 8 figure a-1. overscan compensation, 640x480 ntsc, 20 clock hblank . . . . . . . . . . . . . . . . . . . . . . . . a-2 figure a-2. overscan compensation, 640x480 pal, 20 clock hblank . . . . . . . . . . . . . . . . . . . . . . . . . a-3 figure a-3. overscan compensation, 800x600 ntsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 figure a-4. overscan compensation, 800x600 pal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5
list of figures BT868/bt869 flicker-free video encoder with ultrascale tm technology viii conexant 100123b
BT868/bt869 list of tables flicker-free video encoder with ultrascale tm technology 100123b conexant ix list of tables table 1-1. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 table 1-2. data pin assignments for multiplexed modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 table 1-3. data pin assignments for non-multiplexed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 table 1-4. programmability and frequency requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 table 1-5. auto-configuration modes 0 ? 3 ? rgb input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 table 1-6. auto-configuration modes 4 ? 7 ? ycrcb input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 table 1-7. video modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 table 1-8. video levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 table 2-1. register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 table 2-2. read-back bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 table 2-3. data details defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 table 2-4. programming detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 table 3-1. typical parts list for key passive components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 4-1. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -1 table 4-2. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 table 4-3. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 table 4-4. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table a-1. video formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 table a-2. constant values dependent on encoding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 table a-3. overscan values, 640x480 ntsc, 1 pixel resolution, 2.5 ms hblank . . . . . . . . . . . . . . . . . a-5 table a-4. overscan values, 640x480 ntsc, 8 pixel resolution, 2.5 ms hblank . . . . . . . . . . . . . . . . . a-7 table a-5. overscan values, 640x480 ntsc, 9 pixel resolution, 2.5 ms hblank . . . . . . . . . . . . . . . . . a-8 table a-6. overscan values, 640x480 pal, 1 pixel resolution, 2.5 ms hblank. . . . . . . . . . . . . . . . . . . a-8 table a-7. overscan values, 640x480 pal, 8 pixel resolution, 2.5 ms hblank. . . . . . . . . . . . . . . . . . a-11 table a-8. overscan values, 640x480 pal, 9 pixel resolution, 2.5 ms hblank. . . . . . . . . . . . . . . . . . a-12 table a-9. overscan values, 800x600 ntsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-13 table a-10. overscan values, 800x600, pal, > 2.5 ms hblank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-17
list of tables BT868/bt869 flicker-free video encoder with ultrascale tm technology x conexant 100123b
100123b conexant 1-1 1 1.0 functional description 1.1 pin descriptions the pinout diagram is shown in figure 1-1 . pin names, input/output assignments, numbers and descriptions are listed in tables 1-2 and 1-3 . figure 1-1. pinout diagram reset* vdd vddmax sic p[0] p[1] p[2] p[3] p[4] p[5] p[6] p[7] sid blank* field vsync* hsync* vss p[23] p[22] p[21] p[20] p[19] p[18] sleep agnd vdd_i 80-pin pqfp agnd fsadjust vbias vref comp vaa agnd_dac daca vaa_daca dacb vaa_dacb dacc vaa_dacc clki vdd_co clko vss_co vdd_so vdd_x xtalout xtalin vss_x p[8] p[9] p[10] p[11] p[12] p[13] p[14] p[15] p[16] p[17] pa l slave altaddr vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 nc nc vss vdd vss_i vss_o vdd_o vdd vss_si vss_so 16 17 18 19 20 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 vaa_pll agnd_pll vdd_si n/c n/c n/c test
1.0 functional description BT868/bt869 1.1 pin descriptions flicker-free video encoder with ultrascale tm technology 1-2 conexant 100123b table 1-1. pin assignments (1 of 3) pin name i/o pin # description xtalin i 63 a crystal can be connected to these pins. the pixel clock output (clko) is derived from these pins with a pll. xtalin can be driven as a cmos input pin. xtalout o 62 vdd_x ? 61 crystal oscillator supply pin. this pin should be tied to the digital supply. vss_x ? 64 crystal oscillator ground pin. this pin should be tied to the digital ground plane. vaa_pll ? 59 analog power for pll. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. agnd_pll ? 58 analog ground for pll. all agnd and vss pins must be connected together on the same pcb plane to prevent latchup. clko o 56 pixel clock output (ttl compatible). this pin is three-state if the clki pin provides the encoder clock. vdd_co ? 57 clock output supply pin. this pin should be tied to the digital supply. vss_co ? 55 clock output ground pin. this pin should be tied to the digital ground plane. clki i 54 pixel clock input (ttl compatible). this may be used as either the encoder clock or a delayed version of the clko pin synchronized with the pixel data input. reset* i 53 reset control input (ttl compatible). a logical 0 resets and disables video timing (horizontal, vertical, subcarrier counters to the start of vsync of first field) and resets the serial interface registers). reset* must be a logical 1 for normal operation. sleep i 52 power-down control input (ttl compatible). a logical 1 configures the device for power-down mode. a logical 0 configures the device for normal operation. slave i 51 slave/master mode select input (ttl compatible). a logical 1 configures the device for slave video timing operation. a logical 0 configures the device for master video timing operation. pal i 50 pal/ntsc mode select input (ttl compatible). a logical 1 configures the device for pal video format and mode 1. a logical 0 configures the device for ntsc video format and mode 0. vddmax i 49 input threshold adjustment. this pin should be tied to vdd for 3.3 v input swings and gnd for 5 v input swings. this pin does not affect the serial interface pins (sid and sic). altaddr i 48 alternate slave address input (ttl compatible). a logical 0 configures the device to respond to a serial programming address of 0x88; a logical 1 configures the device to respond to a serial programming address of 0x8a. (1) sic i 45 serial interface clock input (ttl compatible). the maximum clock rate is 400 khz. sid i/o 44 serial interface data input/output (ttl compatible). data is written to and read from the device via this serial bus. vdd_si ? 47 serial interface input supply pin. this pin should be tied to the proper supply voltage for the desired serial interface operating voltage (i.e., tie to 5 v for 5 v serial interface compatibility).
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.1 pin descriptions 100123b conexant 1-3 vss_si ? 42 serial interface input ground pin. this pin should be tied to the digital ground plane. vdd_so ? 46 serial interface output supply pin. this pin should be tied to the proper supply voltage for the desired serial interface operating voltage (i.e., tie to 5 v for 5 v serial interface compatibility). vss_so ? 43 serial interface output ground pin. this pin should be tied to the digital ground plane. test i 39 test pin. should be tied to vss. blank* i/o 38 composite blanking control (ttl compatible). this can be generated by the encoder or supplied from the graphics controller. if internal blanking is used, this pin can be used to indicate the controller character clock edge. field o 37 field control output (ttl compatible) (master mode only three-state in slave mode). field transitions after the rising edge of clk, two clock cycles following falling hsync*. it is a logical 0 during odd fields and is a logical 1 during even fields. vsync* i/o 36 vertical sync input/output (ttl compatible). as an output (master mode operation), vsync* is output following the rising edge of clk. as an input (slave mode operation), vsync* is registered on the rising edge of clk. hsync* i/o 35 horizontal sync input/output (ttl compatible). as an output (master mode operation), hsync* is output following the rising edge of clk. as an input (slave mode operation), hsync* is registered on the rising edge of clk. p[23:0] i 32 ? 34, 23 ? 29, 5 ? 18 pixel inputs. see table 1-2, ? data pin assignments for multiplexed modes, ? on page 1.05 . the input data is sampled on both the rising and falling edge of clk for multiplexed modes, and on the rising edge of clock in non-multiplexed modes. a higher bit index corresponds to a greater bit significance. vdd ? 20,40,60 digital power for core logic. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. vdd_i ? 19 digital power for digital inputs. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. this pin should be tied to the 5 v supply for 5 v tolerant inputs, vdd_o ? 30 digital power for digital outputs. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. vss ? 4, 21, 41 digital ground for core logic. all agnd and vss pins must be connected together on the same pcb plane to prevent latchup. vss_i ? 22 digital ground for inputs. all agnd and vss pins must be connected together on the same pcb plane to prevent latchup. vss_o ? 31 digital ground for outputs. all agnd and vss pins must be connected together on the same pcb plane to prevent latchup. vaa ? 80 analog power. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. agnd ? 1, 79 analog ground. all agnd and vss pins must be connected together on the same pcb plane to prevent latchup. table 1-1. pin assignments (2 of 3) pin name i/o pin # description
1.0 functional description BT868/bt869 1.1 pin descriptions flicker-free video encoder with ultrascale tm technology 1-4 conexant 100123b fsadjust i 78 full-scale adjust control pin. a resistor (rset) connected between this pin and gnd controls the full-scale output current on the analog outputs. vbias o 77 dac bias voltage. a 0.1 f ceramic capacitor must be used to bypass this pin to gnd. the capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. vref o 76 voltage reference pin. a 0.1 f ceramic capacitor must be used to decouple this pin to gnd. the decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. comp o 75 compensation pin. a 0.1 f ceramic capacitor must be used to bypass this pin to vaa. the capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. agnd_dac ? 74 common dac analog ground return. all agnd and vss pins must be connected together on the same pcb plane to prevent latchup. vaa_dacc ? 73 dacc analog power. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. dacc o 72 dacc output. vaa_dacb ? 71 dacb analog power. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. dacb o 70 dacb output. vaa_daca ? 69 daca analog power. all vaa and vdd pins must be connected together on the same pcb plane to prevent latchup. daca o 68 daca output. n/c ? 65, 66, 67 no connect pins note(s): (1) any unused inputs should not be left floating. table 1-1. pin assignments (3 of 3) pin name i/o pin # description
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.1 pin descriptions 100123b conexant 1-5 table 1-2. data pin assignments for multiplexed modes pin rising edge of clki falling edge of clki 24-bit rgb mode 15/16-bit rgb mode 16-bit ycrcb mode 24-bit ycrcb mode 24-bit rgb mode 15/16-bit rgb mode 16-bit ycrcb mode 24-bit ycrcb mode p[11] g4 g2 cr/cb7 cr7 r7 r4 y7 y7 p[10] g3 g1 cr/cb6 cr6 r6 r3 y6 y6 p[9] g2 g0 cr/cb5 cr5 r5 r2 y5 y5 p[8] b7 b4 cr/cb4 cr4 r4 r1 y4 y4 p[7] b6 b3 cr/cb3 cr3 r3 r0 y3 y3 p[6] b5 b2 cr/cb2 cr2 g7 g5 (1) y2 y2 p[5] b4 b1 cr/cb1 cr1 g6 g4 y1 y1 p[4] b3 b0 cr/cb0 cr0 g5 g3 y0 y0 p[3] g0 ?? cb7 r2 ?? cb3 p[2] b2 ?? cb6 r1 ?? cb2 p[1] b1 ?? cb5 r0 ?? cb1 p[0] b0 ?? cb4 g1 ?? cb0 note(s): (1) g5 is ignored in 15-bit rgb mode. table 1-3. data pin assignments for non-multiplexed modes pin 24-bit rgb mode 24-bit ycrcb mode p[23:16] b[7:0] cb[7:0] p[15:8] g[7:0] cr[7:0] p[7:0] r[7:0] cy[7:0]
1.0 functional description BT868/bt869 1.2 gui controller programmability and frequency requirement flicker-free video encoder with ultrascale tm technology 1-6 conexant 100123b 1.2 gui controller programmability and frequency requirement programmability and frequency requirements for the gui controller are defined in table 1-4 . table 1-4. programmability and frequency requirement mode maximum total maximum vsync to active maximum frequencies pixels lines line (khz) pixel (mhz) 640 x 480 1075 665 117 39.860 31.563 800 x 600 1075 835 147 49.451 40.000
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.2 gui controller programmability and frequency requirement 100123b conexant 1-7 figure 1-2 illustrates the concept of flicker filter control. figure 1-2. flicker filter control diagram?external use fifo input in_mode[2:0] 000 = 24-bit f_sely[2:0] 000 = 5 line 001 = 2 line 010 = 3 line 011 = 4 line 100 = alt. 5 line 1 101 = alt. 5 line 2 110 = alt. 5 line 3 111 = alt. 5 line 4 f_selc[2:0] 000 = 5 line 001 = 2 line 010 = 3 line 011 = 4 line 100 = alt. 5 line 1 101 = alt. 5 line 2 110 = alt. 5 line 3 111 = alt. 5 line 4 dis_gmshy ylpf[1:0] 00 = bypass 01 = luma, yat t e n uat e [ 2 : 0 ] 000 = 1.0 gain 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0.0 gain cattenuate[2:0] 000 = 1.0 gain 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0.0 gain flicker filter/scaler 0 = enable luma rgb mux 001 = 16-bit rgb mux 010 = 15-bit rgb mux 011 = 24-bit rgb non-mux 101 = 16-bit ycrcb mux 110 = reserved horizontal lpf1 10 = luma, horizontal lpf2 11 = luma, horizontal lpf3 clpf[1:0] 00 = bypass 01 = chroma, horizontal lpf1 10 = chroma, horizontal lpf2 11 = chroma, horizontal lpf3 ycoring[2:0] 001 = 1/128 of range 010 = 1/64 of range 011 = 1/32 of range 100 = 1/16 of range 101 = 1/8 of range 110 = 1/4 of range 111 = reserved psuedo gamma removal dis_gmshc 0 = enable chroma psuedo gamma removal dis_gmushy 0 = enable luma anti-pseudo gamma removal dis_gmushc 0 = enable chroma anti-psuedo gamma removal dis_yflpf 0 = enable initial luma horizontal low pass filter ccoring[2:0] 001 = +/-1/256 of range 010 = +/- 1/128 of range 011 = +/- 1/64 of range 100 = +/- 1/32 of range 101 = +/- 1/16 of range 110 = +/- 1/8 of range 111 = reserved 000 = bypass 000 = bypass 111 = 24-bit ycrcb non-mux 100 = 24-bit ycrcb mux color space converter
1.0 functional description BT868/bt869 1.2 gui controller programmability and frequency requirement flicker-free video encoder with ultrascale tm technology 1-8 conexant 100123b figure 1-3 illustrates the BT868/869 functional block diagram. figure 1-3. encoder core internal voltage reference 2x fsadjust daca upsample video timing control, reset* lpf u/v modulator 10 and mixer 10 field comp captioning, macrovision closed luma 9 + + dacb 10 dacc 10 out mux out mode 2x upsample x + x bst_amp mcr mcb sync_amp my sync processor burst processor c10 y10 rgb 24 rgb y[9:0] crcb[9:0] 9 cvbs 10 dac dac dac delay to 4:4:4 conversion 4:2:2 registers sid vbias
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-9 1.3 circuit description 1.3.1 overview the BT868/869 is a video encoder designed for tv output of non-interlaced graphics data, such as that found in a pc or some set-top boxes. it incorporates advanced filtering technology for flicker removal and overscan compensation which allows high-quality display of non-interlaced images on an interlaced tv display. the BT868/869 accomplishes this by minimizing the flicker and providing control of the amount of overscan so that the entire image is viewable. the BT868/869 consists of a color space converter/flicker filter engine followed by a digital video encoder. the color space converter/flicker filter contains the following: ?a timing converter various horizontal video processing functions flicker filter and vertical scaler for overscan compensation the output of this engine is fed into a fifo for synchronization with the digital video encoder. 1.3.2 reset if the reset* pin is held low for a minimum of two clock cycles, a timing reset and a software reset is performed. during a timing reset, the serial interface is held in the reset condition, the subcarrier phase is set to zero, and the horizontal and vertical counters are held to the beginning of vsync of field 1 (both counters equal to zero). counting resumes the next clock after rising reset*. the serial interface registers are reset to zero. a software reset, which can be generated by setting the sreset register bit, initializes all the serial interface registers to zero (except for pll_int, which is initialized to 0x0c). as a result, all output pins are three-state. the first 32 registers are then initialized to auto-configuration mode 0 (see the auto configuration section). the en_out bit must be set to enable the outputs. the software reset can also be generated by setting the sreset register bit. a power-on reset is generated on power-up. the power-on reset generates both a timing and a software reset. the power-on reset is generated by a time delay circuit triggered after the supply voltage reaches a value sufficiently high enough for the circuit to operate. as such, the device may not initialize to the default state unless the power supply ramp rate is sufficiently fast enough. therefore, a hardware reset is recommended if the default state is required. 1.3.3 timing registers after writing any registers, a timing reset is recommended by setting the t-bit.
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-10 conexant 100123b 1.3.4 device initialization after a reset condition, the device must be programmed through the serial interface to activate video or output one of the other video standards and to enable the clk0, hsync*, vsync*, and field outputs. 1.3.5 auto configuration the device can configure itself for one of eight combinations of video formats and input modes with a single register write. tables 1-5 and 1-6 detail the eight available auto configuration modes. this feature reduces the software support required, yet allows full flexibility in generating video formats and timing. once the device is configured, all the registers are accessible to modify the modes. for less common modes, the device can be configured for the closest mode, and only those registers that differ need to be programmed. to auto-configure the device, set the configuration bits (config[2:0]) to the desired mode. the device will initialize the first 32 registers (registers 0x3b to 0x5a), setting the busy flag in the process. when complete, the busy flag is cleared. the serial interface is not available when the busy flag is high except for monitoring the status register. if the mux mode is enabled, pins p[23:21] can also be used to externally configure the device to any one of the eight configuration modes. these pins directly emulate the config[2:0] register. in order to configure the device in this way, the en_pincfg register must be set. the desired state must be present on the p[23:21] pins for at least two clock cycles.
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-11 table 1-5. auto-configuration modes 0 ? 3 ? rgb input (1 of 2) register name mode 0 ntsc 640x480 (1 ) clko=28.195793 mhz mode 1 pal 640x480 clko=29.500008 mhz mode 2 ntsc 800x600 clko=38.769241 mhz mode 3 pal 800x600 clko=36.000000 mhz dec hex dec hex dec hex dec hex h_clko [11:0] 1792 700 1888 760 2464 9a0 2304 900 h_active [9:0] 640 280 640 280 800 320 800 320 hsync_width [7:0] 132 84 138 8a 182 b6 170 aa hburst_begin [7:0] 150 96 166 a6 206 ce 202 ca hburst_end [7:0] 96 60 104 68 180 84 154 9a h_blanko [10:0] 381 17d 449 1c1 597 255 525 20d v_blanko [9:0] 34 22 46 2e 32 20 41 29 v_activeo [8:0] 212 d4 242 f2 216 d8 252 fc h_fract [7:0]0000000 0 h_clki [10:0] 784 310 944 3b0 880 370 960 3c0 h_blanki [8:0] 126 7e 266 10a 66 42 140 8c v_blank_dly 0 0 0 0 0 0 0 0 v_linesi [9:0] 600 258 625 271 735 2df 750 2ee v_blanki [7:0] 75 4b 90 5a 86 56 95 5f v_activei [9:0] 480 1e0 480 1e0 600 258 600 258 clpf [1:0] 0000000 0 ylpf [1:0] 3333333 3 v_scale [13:0] 5266 1492 4096 1000 7373 1ccd 5734 1666 pll_fract [15:0] 34830 880e 7282 1c72 15124 3b14 0 0 en_xclk 0 0 0 0 0 0 0 0 by_pll 0 0 0 0 0 0 0 0 pll_int [5:0] 12 c 13 d 17 11 16 10 en_scart 0 0 0 0 0 0 0 0 eclip 0 0 0 0 0 0 0 0 pal 0011001 1 dis_screset 0 0 0 0 0 0 0 0 vsync_dur 1 1 0 0 1 1 0 0 625line 0 0 1 1 0 0 1 1 setup 1100110 0
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-12 conexant 100123b ni_out 0000000 0 sync_amp [7:0] 229 e5 240 f0 229 e5 240 f0 bst_amp [7:0] 118 76 88 58 116 74 87 57 mcr [7:0] 121 79 129 81 119 77 128 80 mcb [7:0] 68447349674372 48 my [7:0] 133 85 140 8c 133 85 140 8c msc [31:0] 545259520 20800000 645499916 26798c0c 396552378 17a2e8ba 528951320 1f872818 note(s): (1) assumes 13.5 mhz clk-d frequency. table 1-5. auto-configuration modes 0 ? 3 ? rgb input (2 of 2) register name mode 0 ntsc 640x480 (1 ) clko=28.195793 mhz mode 1 pal 640x480 clko=29.500008 mhz mode 2 ntsc 800x600 clko=38.769241 mhz mode 3 pal 800x600 clko=36.000000 mhz dec hex dec hex dec hex dec hex table 1-6. auto-configuration modes 4 ? 7 ? ycrcb input (1 of 2) register name mode 4 ntsc 640x480 clko=28.195793 mhz mode 5 pal 640x480 clko=29.500008 mhz mode 6 ntsc 800x600 clko=38.769241 mhz mode 7 pal 800x600 clko=36.000000 mhz dec hex dec hex dec hex dec hex h_clko [11:0] 1792 700 1888 760 2464 9a0 2304 900 h_active [9:0] 640 280 640 280 800 320 800 320 hsync_width [7:0] 132 84 138 8a 182 b6 170 aa hburst_begin [7:0] 150 96 166 a6 206 ce 202 ca hburst_end [7:0] 96 60 103 68 180 b4 154 9a h_blanko [10:0] 381 17d 449 1c1 597 255 525 20d v_blanko [9:0] 34 22 46 2e 32 20 41 29 v_activeo [8:0] 212 d4 242 f2 216 d8 252 fc h_fract [7:0] 0000000 0 h_clki [10:0] 784 310 944 3b0 880 370 960 3c0 h_blanki [8:0] 126 7e 266 10a 66 42 140 8c v_blank_dly 0 0 0 0 0 0 0 0 v_linesi [9:0] 600 258 625 271 735 2df 750 2ee v_blanki [7:0] 75 4b 90 5a 86 56 95 5f v_activei [9:0] 480 1e0 480 1e0 600 258 600 258 clpf [1:0] 0000000 0
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-13 1.3.6 clocking and timing generation there are two timing generators that control the operation of the encoder. the encoder timing block generates the signals for the proper encoding of the video into ntsc or pal, and extracts the processed input pixels from the internal fifo. the encoding timing generator can receive its clock from either an external crystal oscillator and pll, or from the clki pin. normal operation requires that the encoding clock be generated by the pll. the clock source is selected by the en_xclk register bit. if en_xclk is set to a logical 0, the internal clock source is selected; and when the en_out bit is set, the clko pin is enabled to drive the derived clock. a crystal must be present between xtalin and xtalout pins if the internal clock source is selected. the frequency of the clk is synthesized by a pll such that the frequency is: f clk = f xtal * {pll_int(5:0) + [pll_fract(15:0)/216]}/6 ylpf [1:0] 3333333 3 v_scale [13:0] 5266 1492 4096 1000 7373 1ccd 5734 1666 pll_fract [15:0] 34830 880e 7282 1c72 15124 3b14 0 0 en_xclk 0000000 0 by_pll 0 0 0 0 0 0 0 0 pll_int [5:0] 12 c 13 d 17 11 16 10 en_scart 0 0 0 0 0 0 0 0 eclip 0 0 0 0 0 0 0 0 pal 0011001 1 dis_screset 0 0 0 0 0 0 0 0 vsync_dur 1 1 0 0 1 1 0 0 625line 0 0 1 1 0 0 1 1 setup 1100110 0 ni_out 0 0 0 0 0 0 0 0 sync_amp [7:0] 229 e5 240 f0 229 e5 240 f0 bst_amp [7:0] 118 76 88 58 116 74 87 57 mcr [7:0] 121 79 129 81 119 77 128 80 mcb [7:0] 684473 49 67 43 72 48 my [7:0] 133 85 140 8c 133 85 140 8c msc [31:0] 545259520 20800000 645499916 26798c0c 396552378 17a2e8ba 528951320 1f872818 table 1-6. auto-configuration modes 4 ? 7 ? ycrcb input (2 of 2) register name mode 4 ntsc 640x480 clko=28.195793 mhz mode 5 pal 640x480 clko=29.500008 mhz mode 6 ntsc 800x600 clko=38.769241 mhz mode 7 pal 800x600 clko=36.000000 mhz dec hex dec hex dec hex dec hex
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-14 conexant 100123b the crystal must be chosen so that the precise line rate for the video standards required can be achieved. this is done to maintain the subcarrier relationship to the line rate and thereby achieve the precise subcarrier frequency as required by the standard. the crystal oscillator is designed to oscillate from 5-25 mhz. a 13.5 mhz crystal meets the requirements for both ntsc and pal video standards. the crystal must be within 50 ppm of the maximum desired clock rate for ntsc operation, and 25 ppm for pal operation, across temperature (0 to 70 c). see appendix b for list of recommended crystal vendors. the crystal oscillator is disabled by the sleep pin. sufficient time (greater than approximately 1 second) must be allowed after coming out of sleep mode to allow the oscillator to stabilize. if the external clock source is selected (en_xclk=1), a clock signal of the desired pixel clock rate must be present at the clki pin. the clko pin will be three-state, and the crystal oscillator disabled. the clock must meet the same requirements as above. it is highly recommended that the internal clock be used in order to ensure that the output video remain within the specifications defined by the relevant video standard. any aberration in the source clock is reflected in the output video and detracts from the quality of the image. the by_pll bit will bypass the pll, and the encoder clock will be at the crystal frequency. this bit will take precedence over the en_xclk bit. the second timing generator controls the generation of the hsync*, vsync*, blank*, and pixel input clocking. this is normally the same clock as the encoding clock. the en_async register bit, if set, will allow this clock to be driven directly by the clki pin. if the div2 register bit is set, this internal clock is divided by two before driving the second timing generator. this is required for interlaced input to interlaced output mode (i.e., ccir601 applications). the clki pin is the clock used for synchronizing the pixel inputs (p[23:0]) and any timing input signals (hsync*, vsync*, and blank*) and normally must be a delayed version of the clko pin. it can be directly connected to clko if desired. data is registered with this input and re-synchronized to the internal clock. normally, in muxed input mode, both edges of the clki input are used. if the mode2x register bit is set, the internal clock is divided by two, allowing a 2x external clock, and the data to be provided on the rising edge only. 1.3.7 master and slave modes the device can operate as either a timing master or a slave. in master mode, the device will generate and output hsync*, vsync*, and blank*. in slave mode, these must be provided externally. the desired mode is selected by the slave pin and slaver bit. it is highly recommended that the device operate as a master, to ensure that the input and output video streams remain synchronized. if the device supplying the hsync* and vsync* inputs in slave mode is not correctly programmed, or the timing varies from that which is required, the output image will lose lock with the input. by running the device in master mode, any timing errors that occur can be absorbed to some extent by the on-board fifo.
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-15 1.3.8 input formats the device can convert a wide range of input formats to television video formats. the input format can be either non-interlaced computer video in 640 x 480 or 800 x 600 formats, or interlaced formats such as ccir601 formats as well as most other formats which might be encountered. for detailed information on the ccir601 mode, please refer to the ? dvd movie playback architecture and solutions application note ? . this application note may be obtained from your local conexant semiconductor sales office. 1.3.9 pixel input timing the device can accept the input in data either rgb or ycrcb color spaces. data can be input either a full pixel at a time, clocked in on the rising edge of clki, or in various multiplexed modes, using both edges of clki. in ycrcb mode, either 24-bit 4:4:4 data or 16-bit 4:2:2 data can be input. in rgb mode, either 15 bit 5:5:5, 16 bit 5:6:5, or 24-bit rgb can be input. in 16-bit 4:2:2 ycrcb input mode, multiplexed y, cr, and cb data is input through the p[11:4] inputs. the y data is input on the falling edge of clk. the cr/cb data is input on the rising edge of clk. the cb/y/cr/y sequence begins at the first active pixel. in 24-bit 4:4:4 ycrcb input mode, multiplexed y, cr, and cb data is input through the p[11:0] inputs. the input data is sampled on both the rising and falling edge of clk. in rgb input mode, input data is sampled as 12 bits in 24-bit rgb mode or 8 bits in 15/16 bit rgb mode on both the rising and falling edge of clk. table 1-2 shows the assignments of input p[11:0] data on rising edge and falling edge of clk. in addition, all 24-bit modes can utilize a non-multiplexed mode. see table 1-3 on page 1-5 . 1.3.10 output modes the encoder can generate the video as composite/y-c, as yuv component, or as vga-style rgb. these modes are selected by the out_mode[1:0] register bits. when outputting rgb, the device will output vga/svga analog rgb. in this mode, the r, g, and b input data is fed to the dacs after the addition of sync and, if the setup bit is set, setup. the output currents are scaled so that the dacs output the proper 1 v full-scale levels for driving a monitor. the graphics controller provides all the timing control for the monitor, and the device operates as a slave. only the p[23:0], blank*, hsync*, and vsync* input pins and the rgb analog output pins are active. the blank*, hsync*, and vsync* pins are automatically enabled as inputs in this mode. each of the three video signals generated by the out_mode bits can be multiplexed to any dac using the out_muxa[1:0], out_muxb[1:0], and out_muxc[1:0] register bits.
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-16 conexant 100123b 1.3.11 ycrcb inputs y has a nominal range of 16 ? 235; cb and cr have a nominal range of 16 ? 240, with 128 equal to zero. values of 0 and 255 are interpreted as 1 and 254, respectively. y values of 1 ? 15 and 236 ? 254, and crcb values of 1 ? 15 and 241 ? 254, are interpreted as valid linear values. figure 1-4 shows the frequency response of the sub-sampling process. if 4:4:4 data is input, it is sub-sampled to 4:2:2 prior to overscan compensation and flicker filtering. the resulting 4:2:2 output must then be converted to yuv values and then scaled for the output range of the dacs. the my, mcr, and mcb registers must be programmed to perform this conversion. the scaling equations are as follows: my = (int) [v100/(219.0 * vfs) * 2 6 + 0.5] mcr = (int)[(128.0/127.0) * v100 * 0.877/(224.0 * vfs * 0.713 * sinx) * 2 6 + 0.5] mcb = (int)[(128.0/127.0) * v100 * 0.493/(224.0 * vfs * 0.564 * sinx) * 2 6 + 0.5] where:v 100 = 100% white voltage (0.661 v for ntsc, 0.7 v for pal) v fs = full scale output voltage (1.28 v) sinx = sin (2 f sc /f clk )/(2 f sc /f clk ) figure 1-4. decimation filter at fs=27 mhz freq (fs=27mhz decibels (db) chroma decimation filter
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-17 1.3.12 rgb inputs with in_mode set to 24, 16, or 15-bit rgb mode, digital, gamma-corrected rgb data with a 0-255 range is input via the p[11:0] inputs in 24-bit rgb mode or p[11:4] inputs in 15/16-bit rgb mode on both the rising and falling edge of clk. the rgb data is converted to y/r-y/b-y as follows: y[9:0] = [int(.299 * 2 10 ) * r[7:0] + int(.587 * 2 10 ) * g[7:0] + int(.114 * 2 10 ) * b[7:0] = 2 7 ] * 2 ?8 , 0 to 1024 the y/r-y/b-y values are then sub-sampled to 4:2:2 data prior to overscan compensation and flicker filtering. the resulting 4:2:2 output must then be converted to yuv values and then scaled for the output range of the dacs. the my, mcr, and mcb registers must be programmed to perform this conversion. the scaling equations are as follows: my = (int)[v100/(255 * vfs) * 2 6 + 0.5] mcr = (int)[(128.0/127.0) * v100 * 0.877/(127 * vfs * sinx) * 2 5 + 0.5] mcb = (int)[(128.0/127.0) * v100 * 0.493/(127 * vfs * sinx) * 2 5 + 0.5] where:v 100 = 100% white voltage (0.661 v for ntsc, 0.7 v for pal) v fs = full scale output voltage (1.28 v) sinx = sin (2 f sc /f clk )/(2 f sc /f clk ) 1.3.13 video amplitude scaling both the luminance and chrominance video amplitudes can be scaled by the mcr, mcb, and my registers. this allows various colormetry standards to be achieved, and can also be used to boost the chroma to compensate for the sinx/x loss of the dacs. tables 1-7 and 1-8 show the range of values achievable and values for various video formats. table 1-7. video modes mode ntsc ntsc-japan pal-bdghi pal-n pal-nc pal-m pal-60 vsync_dur 1 1 0 1 0 1 1 625line 0 0 1 1 1 0 0 setup 1 0 0 1 0 1 0 pal 0 0 1 1 1 1 1
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-18 conexant 100123b 1.3.14 input pixel horizontal sync the hsync* pin provides the pixel synchronization for the pixel input data. it is an output in master mode, and an input in slave mode. in master mode, it is a pulse two clk cycles in duration whose leading edge indicates the beginning of a new line of pixel data. the period of the pulses is h_clki clk cycles. the first pixel should be presented to the device h_blanki minus the internal pipelined clock (in clk cycles) after a leading edge of hsync*. the next h_active pixels will be accepted as active pixels and used in the construction of the output video. in slave mode, the period must be exactly the number of clocks required for the desired overscan mode. only the leading edge is used, and the high and low times must be at least two clk cycles in duration. hsync* is clocked by the rising edge of clki. hsynci is clocked by the rising edge of clki. the polarity of the hsync* pin can be programmed by the hsynci register bit. the default convention is active low. table 1-8. video levels mode range n t s c ntsc- japan palbdghi pal-n pal-nc pal-m pal-60 100% white amp (v) 0.661 0.714 0.7 0.661 0.7 0.661 0.7 sync amp (v) 0.286 0.286 0.301 0.286 0.301 0.286 0.301 subcarrier amp (v) 0.286 0.286 0.3 0.3 0.3 0.306 0.306 ycrcb input my 0 ? 255 153 158 158 153 158 153 158 mcr 0-255 187 207 207 187 207 187 207 mcb 0-255 133 149 149 133 149 133 149 rgb input my 0 ? 255 133 143 141 133 141 133 141 mcr 0-255 117 127 124 117 124 117 124 mcb 0-255 66 71 70 66 70 66 70 sync_amp 0 ? 255 225 225 238 225 238 225 238 bst_amp 0 ? 255 114 114 90 90 90 92 92
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-19 1.3.15 input pixel vertical sync the vsync* pin provides the line synchronization for the pixel input data. it is an output in master mode, and an input in slave mode. for non-interlaced input timing in master mode, vsync* is a pulse one horizontal line time in duration whose leading edge indicates the beginning of a frame of input pixel data. the leading edge coincides with the leading edge of hsync*. the period of the pulses is v_linesi horizontal lines. the first line of data should be presented to the device v_blanki lines after the leading edge of vsync*. the next v_activei lines are accepted as active lines and used in the construction of the output video. in slave mode, the period must be exactly the frame rate of the desired video format. only the leading edge is used, and the high and low duration must be at least two clk cycles. the beginning of the frame of data is indicated by the next leading edge of hsync* coincident with or after the leading edge of vsync*. for interlaced input timing, only slave mode is supported. the period must be exactly the frame rate of the desired video format. if the leading edge of hsync* and vsync* are coincident, which indicates the input is in odd field, the internal line counter is reset to line 1 at the leading edge of vsync*. if the leading edges of hsync* and vsync* are not coincident, which indicates the input is in even field, the internal line counter will be reset to line 2 at the beginning of the next line. only the leading edge of vsync* is used, and the high and low duration must be at least two clk cycles. vsync* is clocked by the rising edge of clki. the polarity of the vsync* output can be programmed by the vsynci register bit. the default convention is active low. 1.3.16 input pixel blanking the input pixel blanking can be controlled by either the blank* pin or by the internal registers. it can be programmed independently of master/slave mode using the en_blanko register bit. in output mode (en_blanko=1), the pixel blanking is generated based on the active area defined by the h_blanki, h_active, v_blanki, and v_activei registers, and the blank* pin will be output in the proper relationship to the syncs to indicate the active pixels. in input mode (en_blanko=0), when the blank* pin goes high, it will indicate start of active pixels at the pixel input pins. the duration of active pixel is still determined by the h_active register. blank* is clocked by the rising edge of clki. an additional function for the blank* pin is used if the en_dot register bit is set. in this mode, the internally-generated blanking is used. the blank* pin becomes an input whose rising edge defines the graphics controller character clock boundary. this is used internally by the encoder to keep track of the exact pixel count for controllers that cannot operate at pixel clock rates but instead operate at vga character clock rates.
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-20 conexant 100123b 1.3.17 overscan compensation and flicker filtering the resulting subsampled and optionally color-space-converted pixel data is processed by the overscan compensation and flicker filtering logic. this process converts the lines of input pixel data to the appropriate number of output lines for producing a full-screen image on the television receiver. the image, which is 100% within the viewable area of the screen (overscan compensated), can perform vertical filtering to reduce the effects of picture flicker due to the interlacing of the output image. the amount of flicker filtering is programmable, because this process trades off vertical resolution in order to reduce the flicker, and allows the process to be optimized for the image. horizontal scaling is achieved by adjusting the encoder clock rate. no additional horizontal processing is performed on the input pixels. this allows the full bandwidth of the input image to be output, limited only by the 2x upsampling filter response, which is nominally greater than 6 mhz. the device can accept a wide variety of input image formats, from 640x480 to 800x600, and can output all ntsc and pal video formats. figures a-1 through a-4 in appendix a show the possible ranges of overscan compensation for 640x480 and 800x600 ntsc and pal formats, for graphics controllers with synchronization resolutions of 1, 8, and 9 pixel clocks, using a horizontal blanking interval of 20 pixel clocks. tables a-3 through a-10 show representative values for the following: input picture and frame and output picture and field sizes for 640x480 and 800x600 input picture size ntsc and pal outputs using a horizontal blanking interval of 2.5 s. the dis_ffilt register bit disables the flicker filter. the vertical scaling should also be disabled by setting the vscale register to 4096 for non-interlaced input, or 0 for interlaced input. config[2:0] this field determines the configuration for the automatic configuration process. 000 = ntsc 640 x 480 rgb input 001 = pal 640 x 480 rgb input 010 = ntsc 800 x 600 rgb input 011 = pal 800 x 600 rgb input 100 = ntsc 640 x 480 ycrcbycrcb input 101 = pal 640 x 480 ycrcb input 110 = ntsc 800 x 600 ycrcb input 111 = pal 800 x 600 ycrcb input lumadly[1:0] this 2-bit value can be used to program the luminance delay in pixels for the cvbs_dly and y_dly output modes. 00 = no delay 01 = 1 pixel 10 = 2 pixels 11 = 3 pixels
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-21 1.3.18 vga compatibility to achieve vga compatibility, the controller must manipulate the vga register settings in order to produce a consistent output timing for all vga modes. the encoder has no way of knowing that a different vga mode has been selected, and therefore cannot make any adjustments to the timing. the extent of vga compatibility is entirely the controller ? s responsibility. 1.3.19 analog horizontal sync the duration of the horizontal sync pulse is determined by the horizontal sync width register (hsync_width[7:0]). the beginning of the horizontal sync pulse corresponds to the reset of the internal horizontal pixel counter. the horizontal line rate is determined by h_clki[11:0]. the internal horizontal counter is reset to 1 at the beginning of the horizontal sync and counts up to h_clki. the sync rise and fall times are automatically controlled. the sync amplitude is programmable over a range of values by sync_amp[7:0]. table 1-8 lists the range of sync values obtainable and the preferred values for various video formats. 1.3.20 analog vertical sync the duration of the vertical sync is selectable as either 2.5 or 3 lines by register bit vsync_dur. if vsync_dur = 0, 3 lines are selected; if vsync_dur = 1, 2.5 lines are selected. the duration of the serration and equalization pulses are 1/2 the duration of the horizontal sync duration. 1.3.21 analog video blanking analog video blanking is controlled by the h_blanko, v_blanko, and v_activeo registers. together they define an active region where pixels will be displayed. v_blanko defines the number of lines from the leading edge of the analog vertical sync to the first active output lines, per field; v_activeo defines the number of active output lines. h_blanko defines the number of output pixels from the leading edge of horizontal sync to the first active output pixel; h_blanko defines the number of active output pixels. the device will automatically blank the video from the start of the horizontal sync interval through the end of the burst, as well as the vertical sync to prevent erroneous video timing generation. 1.3.22 video standards there are several bits (625line, setup, and vsync_dur) and a pal pin that control the generation of various video standards. (these are summarized in table a-1 .) they allow the generation of all the ntsc and pal video standards. these bits control the specific encoding process parameter, and other registers may also need to be modified to meet all the video parameters of the particular video standard. video timing diagrams are illustrated in figures 1-5 through 1-13 , which summarize all the common video standards and the required register values for typical input formats.
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-22 conexant 100123b figure 1-5. interlaced 525-line (ntsc) video timing note(s): smpte line numbering convention is used rather than ccir624. 22 7 6 5 4 3 burst phase 2 1 525 524 523 analog field 1 start of vsync analog field 2 272 271 270 269 268 267 263 262 261 266 265 264 285 analog field 3 burst phase analog field 4 burst begins with positive half-cycle burst phase = reference phase = 180 relative to b ? y burst begins with negative half-cycle burst phase = reference phase = 180 relative to b ? y 89 10 22 7 6 5 4 3 2 1 525 524 523 89 10 272 271 270 269 268 267 263 262 261 266 265 264 285 reset*
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-23 figure 1-6. interlaced 525-line (pal-m) video timing 22 7 6 5 4 3 burst phase 2 1 525 524 523 analog field 1 start of vsync* analog field 2 272 271 270 269 268 267 263 262 261 266 265 264 analog field 3 burst phase analog field 4 89 10 7 6 5 4 3 2 1 525 524 523 89 272 271 270 269 268 267 263 262 261 266 265 264 burst phase = reference phase = 135 relative to u pal switch = 0, +v component burst phase = reference phase + 90 = 225 relative to u pal switch = 1, ? v component 11 12 22 11 12 285 274 273 285 274 273 10 reset*
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-24 conexant 100123b figure 1-7. interlaced 625-line (pal ? b, d, g, h, i, nc) video timing (fields 1 ? 4) 24 7 6 5 4 3 ? u phase 2 1 622 621 620 analog field 1 start of vsync 625 624 623 23 analog field 2 337 320 318 317 316 315 314 309 308 312 311 336 319 337 320 317 316 315 314 308 313 312 311 336 319 310 313 309 318 310 24 7 6 5 4 3 2 1 622 621 620 625 624 623 23 field one field two field three field four burst blanking intervals burst phase = reference phase = 135 relative to u pal switch = 0, +v component burst phase = reference phase + 90 = 225 relative to u pal switch = 1, ? v component analog field 3 analog field 4 reset*
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-25 figure 1-8. interlaced 625-line (pal ? b, d, g, h, i, nc) video timing (fields 5 ? 8) 24 7 6 5 4 3 ? u phase 2 1 622 621 620 analog field 5 start of vsync 625 624 623 23 337 320 318 317 316 315 314 309 308 312 311 336 319 337 320 317 316 315 314 308 313 312 311 336 319 310 313 309 318 310 24 7 6 5 4 3 2 1 622 621 620 625 624 623 23 field five field six field seven field eight burst blanking intervals burst phase = reference phase = 135 relative to u pal switch = 0, +v component burst phase = reference phase + 90 = 225 relative to u pal switch = 1, ? v component analog field 6 analog field 7 analog field 8 reset*
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-26 conexant 100123b figure 1-9. interlaced 625-line (pal ? n) video timing (fields 1 ? 4) 24 7 6 5 4 3 2 1 622 621 620 625 624 623 23 337 320 318 317 316 315 314 309 308 312 311 336 337 320 317 316 315 314 308 313 312 311 336 24 7 5 4 3 2 1 621 620 625 624 623 23 ? u phase analog field 1 analog field 2 field one field two field three field four burst blanking intervals burst phase = reference phase = 135 relative to u pal switch = 0, +v component burst phase = reference phase + 90 = 225 relative to u pal switch = 1, ? v component analog field 3 analog field 4 reset* vsync* 310 309 622 310 313 319 6 318 319
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-27 figure 1-10. interlaced 625-line (pal ? n) video timing (fields 5 ? 8) 24 7 6 5 4 3 ? u phase 2 1 622 621 620 625 624 623 23 337 320 318 317 316 315 314 309 308 312 311 336 319 337 320 317 316 315 314 308 313 312 311 336 319 310 313 309 318 310 24 7 6 5 4 3 2 1 622 621 620 625 624 623 23 field five field six field seven field eight burst blanking intervals burst phase = reference phase = 135 relative to u pal switch = 0, +v component burst phase = reference phase + 90 = 225 relative to u pal switch = 1, ? v component analog field 6 analog field 7 analog field 8 analog field 5 vsync*
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-28 conexant 100123b figure 1-11. noninterlaced 262-line (ntsc) video timing 10 21 9 8 7 6 5 4 3 field 1 2 1 262 261 start of vsync 263 524 523 268 267 266 265 264 272 271 270 269 burst begins with positive half-cycle burst phase = reference phase = 180 relative to b-y burst begins with negative half-cycle burst phase = reference phase = 180 relative to b-y 285 start of vsync field 2 figure 1-12. noninterlaced 262-line (pal ? m) video timing burst begins with positive half-cycle burst phase = reference phase = 180 relative to b-y burst begins with negative half-cycle burst phase = reference phase = 180 relative to b-y 10 21 9 8 7 6 5 4 3 285 272 271 270 269 268 267 2 1 525 524 start of vsync 266 265 264 263 262 274 11 12 273 field 1 field 2 start of vsync
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-29 1.3.23 subcarrier generation the device uses a 32-bit-word to synthesize the subcarrier. the value of the subcarrier increment required to generate the desired subcarrier frequency is found with the following equation: msc[31:0] = (int) (2 32 * f sc / f clk + 0.5) or more directly, for ntsc: msc[31:0] = 2 32 * [455 * / (2 * h_clko)] and for pal: msc[31:0] = 2 32 * [(1135/4 + 1/625) / (h_clko)] where f clk is the encoder clock rate. this allows the generation of any desired subcarrier to enable the generation of any desired video standard. the 32-bit subcarrier increment msc[31:0] must be loaded by the serial interface before the subcarrier can be enabled. the device is reset to disable chroma until the last byte of the 32-bit increment is loaded, at which time the chroma will be enabled, unless the dchroma bit is set. in order to prevent any residual errors from accumulating, the subcarrier dto (discrete time oscillator) is reset every four fields for ntsc formats and every eight fields for pal formats. figure 1-13. noninterlaced 312-line (pal ? b, d, g, h, i, n, nc) video timing 23 7 6 5 1 312 311 310 309 308 start of vsync 23 4 reset* 24 23 7 6 5 1 312 311 310 309 308 23 4 24 burst phase = reference phase = 135 relative to u pal switch = 0, +v component burst phase = reference phase + 90 = 225 relative to u pal switch = 1, ? v component
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-30 conexant 100123b 1.3.24 burst generation the subcarrier burst generation is a function of the video standard (e.g. ntsc or pal), the subcarrier frequency increment (msc[31:03]), and the burst horizontal begin and end register settings (hburst_begin[7:0] and hburst_end[7:0]). the value of hburst_begin[7:0] and hburst_end[7:0] is the desired pixel minus a value of 128. the burst will automatically be blanked during the horizontal sync to prevent invalid sync pulses from being generated. the burst blanking is automatically controlled by the selected video format. the burst rise and fall times are automatically generated by the device. the burst amplitude can be programmed by bst_amp[5:0]. table 1-8 shows the ranges of burst values obtainable and the preferred values for various video formats. 1.3.25 chrominance disable the chrominance subcarrier can be turned off by setting the dchroma bit to a logical 1. this kills burst as well, providing luminance-only signals on the cvbs output and a static blank level on the c/r output. 1.3.26 digital processing once the input data is converted into internal yuv format, the uv components are low-pass filtered with a filter response illustrated in figure 1-14 (linearly scalable by clock frequency). the y and filtered uv components are upsampled to clk frequency by a digital filter whose response is illustrated in figure 1-15 . figure 1-14. three-stage chroma filter 5 0 ? 5 ? 15 ? 20 ? 25 ? 30 ? 35 ? 40 ? 10 frequency mhz attenuation db 0 0.5 1 1.5 2 clk = 27 mhz
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-31 1.3.27 subcarrier phasing in order to maintain correct sc-h phasing, subcarrier phase is set to 0 on the leading edge of the analog vertical sync every four (ntsc) or eight (pal) fields, unless the dis_screset bit is set to a logical 1. this is true for both interlaced and non-interlaced outputs. the subcarrier phase can be adjusted from the nominal 0 phase by the phase_off[7:0] register, where each lsb change corresponds to a 360/256 degree change in the phase. setting dis_screset to 1 may be useful in situations where the ratio of clk/2 to hsync* edges in a color frame is noninteger, which could produce a significant phase impulse by resetting to 0. 1.3.28 noninterlaced operation when the BT868/869 is programmed for noninterlaced master mode, it always displays the odd field. field will change state on the leading edge of the analog vertical sync. a 30 hz offset should be subtracted from the color subcarrier frequency while in ntsc mode so that the color subcarrier phase will be inverted from field to field. transition from interlaced to noninterlaced in master mode occurs during odd fields to prevent synchronization disturbance. note: consumer vcrs can record noninterlaced video with minor noise artifacts, but special effects (e.g., scan > 2x) may not function properly. figure 1-15. luminance upsampling filter response 5 0 ? 5 ? 15 ? 20 ? 25 ? 30 ? 35 ? 40 ? 10 frequency mhz attenuation db 0612 24 810 (internal encoder clk = 27 mhz)
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-32 conexant 100123b 1.3.29 closed captioning the BT868/869 encodes ntsc/pal ? m closed captioning on scan line 21, and ntsc/pal ? m extended data services on scan line 284. four 8-bit registers (ccf1b1, ccf1b2, ccf2b1, and ccf2b2) provide the data while bits eccf1 and eccf2 enable display of the data. a logical 0 corresponds to the blanking level of 0 ire, while a logical 1 corresponds to 50 ire above the blanking level. closed captioning for pal ? b, d, g, h, i, n, nc is similar to that for ntsc. closed-caption (cc) encoding is performed for 625-line systems according to the system proposed by the national captioning institute; clock and data timing is identical to that of ntsc system, except that encoding is provided on lines 22 and 335, for closed captioning and extended data services respectively. the BT868/869 generates the clock run-in and appropriate timing automatically. pixel inputs are ignored during cc encoding. see fcc code of federal regulations (cfr) 47 section 15.119 (10/91 edition or later) for programming information. eia608 describes ancillary data applications for field 2 line 21 (line 284). when ccf1b2 is written, ccstat_o is set; when ccf2b2 is written, ccstat_e is set. after the cc bytes for the odd field are encoded, ccstat_o is cleared; after the cc bytes for the even field are encoded, ccstat_e is cleared. if the eccgate bit is set, no further encoding will be performed until the appropriate registers are again written; a null will be transmitted on the appropriate cc line in that case. if the eccgate bit is not set, the user must rewrite the cc registers prior to reaching the cc line; otherwise the last bytes will be re-encoded. the cc data bytes are double-buffered to prevent loss of data during the encoding process. 1.3.30 internal color bars the BT868/869 can be configured to generate 100% amplitude, 75% saturation (100/7.5/75/7.5 for ntsc/pal-m with setup, 100/0/75/0 for pal) color bars. color bars can be enabled or disabled by setting the ecbar bit to a logical 1. the device uses the h_blanko register value to determine the starting point of the color bars, and the h_active register value to determine the width. eight bars are displayed, with the colors and amplitudes being generated internally. the pixel inputs are ignored in color bar mode. the my, mcr, and mcb registers must be programmed for rgb inputs prior to color bar operation. 1.3.31 macrovision encoding the bt869 device supports version 7.xx of the macrovision specification for copy protection for all ntsc and pal modes. the BT868 does not support the macrovision feature.
BT868/bt869 1.0 functional description flicker-free video encoder with ultrascale tm technology 1.3 circuit description 100123b conexant 1-33 1.3.32 outputs there are four modes for the analog outputs, selected by out_mode[1:0]. the first mode (out_mode=0) generates composite video (cvbs), luma (y), chroma (c), and delayed luma (y_dly). the second mode (out_mode=1) generates luma-delayed composite video (cvbs_dly), luma (y), chroma (c), and delayed luma (y_dly). the third mode (out_mode=2) generates component yuv and delayed luma (y_dly). the fourth mode (out_mode=3) generates vga-style rgb outputs. the lumadly[1:0] register bits control the amount of delay for the delayed luma, from 0 to 3 pixel clocks. for each mode, any of the four generated outputs can be muxed to any of three output dacs by the register bits out_muxa[1:0], out_muxb[1:0], and out_muxc[1:0]. all digital-to-analog converters are designed to drive standard video levels into a combined rload of 37.5 ? (doubly-terminated 75 ? ). unused outputs should be disabled by setting the corresponding dacdisx bit to minimize supply current, or connected directly to ground to minimize supply switching currents. 1.3.33 output connection status the device can determine whether or not the dac output is connected to a monitor by verifying that the output is doubly-terminated. the monstatx bit for the corresponding dac is set to a 1 if the device senses a doubly-terminated load on a reset condition or if the check_stat register bit is set. while check_stat is set, the output is forced to 2/3 of vref when terminated and 4/3 of vref if unterminated. the monstatx bit reflects the condition when the dac output is less than or equal to vref. the check_stat bit is automatically cleared after two clock cycles. 1.3.34 output filtering and sinx/x compensation the dac output response is a typical sinx/x response. for the composite video output, this results in a slightly lower than desired burst and chroma amplitude value. this can be compensated for, to some extent, by choosing an output filter which boosts higher frequency response slightly. another method which can be used effectively, and is used by default in the auto configuration modes, is to boost the burst and chroma gain as programmed by the bst_amp and mcr/mcb register values by x/sinx. the amount of sinx/x amplitude reduction is calculated by: sinx/x = sin ( * fsc/fclk) / ( * fsc/fclk)
1.0 functional description BT868/bt869 1.3 circuit description flicker-free video encoder with ultrascale tm technology 1-34 conexant 100123b 1.3.35 power-down modes the device can be placed in a low-power mode by the sleep pin. in this mode, the analog circuitry is shut down, disabling the output video, and the internal clock to the device is held constant, placing both the analog and digital current draw to a minimum. register states are preserved, but other chip functionality (including the serial interface) is disabled. this mode achieves the greatest reduction in power. in addition, the entire analog subsection can be powered-down with the dacoff bit, allowing digital operations to continue while reducing the power in the analog circuitry. this will achieve a significant reduction in power while maintaining all digital functionality. each individual dac can also be powered down by its corresponding dacdisx bit. this is useful only if some of the dacs are being used, in order to minimize the power in the system. 1.3.36 serial interface the device includes a 2-wire serial interface which is used for programming the registers in the device. the interface is designed to operate with either 3.3 v or 5 v input levels by changing the supply voltage for the input and output drivers with the vdd_si pin.
100123b conexant 2-1 2 2.0 internal registers a register bit map is displayed in table 2-1 , and a read-back bit map is displayed in table 2-2 . bit descriptions and detailed programming information follow the bit map. all registers are write-only and are set to 0 following a software reset. a software reset is always performed at power-up; after power-up, a reset can be triggered by writing the sreset register bit. table 2-1. register bit map (1 of 3) 8-bit address d7 d6 d5 d4 d3 d2 d1 d0 6c timing reset reserved 6e hsynoffset[7:0] 70 hsynoffset[9:8] hsynwidth[5:0] 72 vsynoffset[7:0] 74 datdly datswp vsynoffset[10:8] vsynwidth[2:0] 76 h_clko[7:0] 78 h_active[7:0] 7a hsync_width[7:0] 7c hburst_begin[7:0] 7e hburst_end[7:0] 80 h_blanko[7:0] 82 v_blanko[7:0] 84 v_activeo[7:0] 86 v_activeo[8] reserved h_active[9:8] h_clko[11:8] 88 h_fract[7:0] 8a h_clki[7:0] 8c h_blanki[7:0] 8e reserved reserved reserved vblankdly h_blanki[8] h_clki[10:8] 90 v_linesi[7:0] 92 v_blanki[7:0] 94 v_activei[7:0] 96 clpf[1:0] ylpf[1:0] v_activei[9:8] v_linesi[9:8]
2.0 internal registers BT868/bt869 flicker-free video encoder with ultrascale tm technology 2-2 conexant 100123b 98 v_scale[7:0] 9a h_blanko[9:8] v_scale[13:8] 9c pll_fract[7:0] 9e pll_fract[15:8] a0 en_xclk by_pll pll_int[5:0] a2 reserved eclip pal_md dis_screset vsync_du r 625line setup ni_out a4 sync_amp[7:0] a6 bst_amp[7:0] a8 mcr[7:0] aa mcb[7:0] ac my[7:0] ae msc[7:0] b0 msc[15:8] b2 msc[23:16] b4 msc[31:24] b6 phase_off[7:0] b8 en_pincfg config[2:0] ba sreset check_stat slaver dacoff reserved dacdis c dacdisb dacdisa bc ccf2b1[7:0] be ccf2b2[7:0] c0 ccf1b1[7:0] c2 ccf1b2[7:0] c4 estatus[1:0] eccf2 eccf1 eccgate ecbar dchrom a en_out c6 en_blanko en_dot fieldi vsynci hsynci in_mode[2:0] c8 dis_yflpf dis_ffilt f_selc[2:0] f_sely[2:0] ca dis_gmushy dis_gmshy ycoring[2:0] yattenuate[2:0] cc dis_gmushc dis_gmshc ccoring[2:0] cattenuate[2:0] ce reserved out_muxc[1:0] out_muxb[1:0] out_muxa[1:0] d0 ccr_start[7:0] d2 cc_add[7:0] d4 mode2x div2 en_async ccr_start[8] cc_add[11:8] table 2-1. register bit map (2 of 3) 8-bit address d7 d6 d5 d4 d3 d2 d1 d0
BT868/bt869 2.0 internal registers flicker-free video encoder with ultrascale tm technology 2.1 essential registers 100123b conexant 2-3 2.1 essential registers the power-up state is defined to be black burst ccir601 ntsc video. to enable active video, the en_out register bit must be set. this bit enables clko, hsync*, vsync*, blank*, and field outputs. if this bit is not set, then these pins are set to a high impedance. 2.2 writing addresses following a start condition, writing 0x88 initiates access to subaddresses. alternative address 0x8a must be written if the altaddr pin is high. if the data is written in subaddress order, only the beginning subaddress needs to be written; the internal address counter will automatically increment after each write to a register. 2.3 reading information following a start condition, writing 0x89 initiates the read-back sequence, during which 8 bits of information can be read from the sid pin, msb first. alternative address 0x8b is required if the altaddr pin is high. for the case of estatus[1:0]=00 prior to the read sequence, the first three bits indicate the part type (BT868 or bt869). the lower five bits indicate the version number or the status bits. the instances where estatus[1:0]=01 and estatus[1:0]=10, the bits read back from the vga encoder will contain information as specified by table 2-2 . for software detection of a connected tv monitor on each dac output, estatus[1:0] must equal 01 and the monstat x bits should be read accordingly after writing to check_stat. data details are defined in table 2-3 ; bit and register definitions are displayed in table 2-4 . d6 reserved reserved reserved reserved out_mode[1:0] lumadly[1:0] d8 reserved table 2-1. register bit map (3 of 3) 8-bit address d7 d6 d5 d4 d3 d2 d1 d0
2.0 internal registers BT868/bt869 2.3 reading information flicker-free video encoder with ultrascale tm technology 2-4 conexant 100123b table 2-2. read-back bit map estatus[1:0] 7 6 5 4 3 2 1 0 00 id[2:0] version[2:0] 01 monstat_ a monstat_b monstat_c ccstat_e ccstat_o field[2:0] 10 pll_lock fifo_over fifo_under pal busy table 2-3. data details defined bit names data definition id[2:0] indicates the part number: 000 is returned from the BT868; 001 is returned from the bt869. version[4:0] version number; for this revision, these bits are 00001. monstat_a monitor connection status for daca output, 1 denotes monitor connected to daca. monstat_b monitor connection status for dacb output, 1 denotes monitor connected to dacb. monstat_c monitor connection status for dacc output, 1 denotes monitor connected to dacc. ccstat_e high if closed-caption data has been written for the even field; it is low immediately after the clock run-in on line 21(ntsc) or 22(pal). ccstat_o high if closed-caption data has been written for the odd field; it is low immediately after the clock run-in on line 284(ntsc) or 335(pal). field[2:0] field number, where 000 indicates the first field, 111 indicates the 8th field. pll_lock high when pll is locked. fifo_over set to one if fifo overflows. reset on read. fifo_under set to one if fifo underflows. reset on read. pal indicates status of pal pin. busy indicates that the device is in the process of initializing the registers and that the registers cannot be written. this bit remains high for 512 clk-0 after an auto configuration cycle begins. table 2-4. programming detail (1 of 7) bit/register names bit/register definition h_clko[11:0] number of output clks/line h_active[9:0] number of active input and output pixels hsync_width[7:0] analog sync width in clocks hburst_begin[7:0] beginning of burst 50% point in number of clock cycles from analog hsync falling edge hburst_end[7:0] end of burst 50% point in number of clock cycles ? 128 from analog sync falling edge h_blanko[9:0] number of output clks between leading edge of horizontal sync and active video v_blanko[7:0] line number of first active line (number of blank lines + 1) v_activeo[8:0] number of active output lines/field
BT868/bt869 2.0 internal registers flicker-free video encoder with ultrascale tm technology 2.3 reading information 100123b conexant 2-5 h_fract[7:0] fractional number of input clocks per line h_clki[10:0] number of clocks per line between successive hsync* edges h_blanki[8:0] number of input pixels between hsync* leading edge and first active pixel vblankdly if set, the effective vertical blanking value in the second field is v_blanki+1. v_linesi[9:0] number of vertical input lines v_blanki[7:0] number of input lines between vsync* leading and first active line v_activei[9:0] number of active input lines clpf[1:0] chroma horizontal low pass filter 00 = bypass 01 = reserved 10 = chroma horizontal lpf2 11 = chroma horizontal lpf3 ylpf[1:0] luma post-flickerfilter/scaler horizontal low pass filter 00 = bypass 01 = luma horizontal lpf1 10 = luma horizontal lpf2 11 = luma horizontal lpf3 v_scale[13:0] vertical scaling coefficient pll_fract[15:0] fractional portion of pll multiplier pll_int[5:0] integer portion of pll multiplier en_xclk 0 = encoder generates pixel clock 1 = use clki pin as pixel clock source by_pll 0 = use pll 1 = bypass pll (encoder clock is crystal frequency) reserved reserved for future software compatibility; should be set to zero for normal operation. eclip 0 = normal operation 1 = enable clipping; dac values less than 31 are made 31 pal_md video output switch bit. if pal pin = 0, this controls analog output format 0 = changes video output to ntsc mode 1 = changes video output to pal mode (even if pal pin = 0) dis_screset 0 = normal operation. the subcarrier phase is reset to 0 at the beginning of each color field sequence 1 = disables subcarrier reset event at beginning of field sequence vsync_dur 0 = generates 2.5-line vsync analog output 1 = generates 3-line vsync analog output 625line 0 = 525-line format 1 = 625-line format setup 1 = setup on. the 7.5 ? ire setup is enabled for active video lines. 0 = setup off. the 7.5 ? ire setup is disabled for active video lines. ni_out 0 = interlaced analog video output 1 = noninterlaced analog video output table 2-4. programming detail (2 of 7) bit/register names bit/register definition
2.0 internal registers BT868/bt869 2.3 reading information flicker-free video encoder with ultrascale tm technology 2-6 conexant 100123b sync_amp[7:0] multiplication factor for sync amplitude bst_amp[7:0] burst amplitude multiplication factor mcr[7:0] multiplication factor for cr (or r-y) component prior to subcarrier modulation mcb[7:0] multiplication factor for cb (or b-y) component prior to subcarrier modulation my[7:0] multiplication factor for y component msc[31:0] subcarrier increment phase_off[7:0] subcarrier phase offset en_pincfg when set, this will enable the auto configuration to be controlled by p[23:21]. whenever a change is detected on these pins, the mode is reconfigured. this field determines the configuration for the automatic configuration process config[2:0] 000 = ntsc 640x480 rgb input 001 = pal 640x480 rgb input 010 = ntsc 800x600 rgb input 011 = pal 800x600 rgb input 100 = ntsc 640x480 ycrcb input 101 = pal 640x480 ycrcb input 110 = ntsc 800x600 ycrcb input 111 = pal 800x600 ycrcb input sreset writing a 1 to this bit performs a software reset; all registers are reset to 0s unless the config[2:0] field is non-0; in that case, the automatic configuration process is begun and the busy status bit is set. this bit is automatically cleared. check_stat writing a 1 to this bit checks the status of the monitor connections at the dac output. this is also automatically performed on any reset condition, including a software reset. this bit is automatically cleared. dacoff 0 = normal operation 1 = disables dac output current and internal voltage reference. this will limit power consumption to just the digital circuits. dacdisc 0 = normal operation 1 = disables dac output. current is set to 0; output will go to 0 v. dacdisb 0 = normal operation 1 = disables dacb output. current is set to 0; output will go to 0 v. dacdisa 0 = normal operation 1 = disables daca output. current is set to 0; output will go to 0 v. ccf2b1[7:0] this is the first byte of closed-caption information for the even field, line 284 for ntsc or line 335 for pal. data is encoded lsb first. ccf2b2[7:0] this is the second byte of closed-caption information for the even field, line 284 for ntsc or line 335 for pal. data is encoded lsb first. ccf1b1[7:0] this is the first byte of closed-caption information for the odd field, line 21 for ntsc or line 22 for pal. data is encoded lsb first. ccf1b2[7:0] this is the second byte of closed-caption information for the odd field, line 21 for ntsc or line 22 for pal. data is encoded lsb first. estatus[1:0] serial read-back status bit selection. (see table 2-2 .) table 2-4. programming detail (3 of 7) bit/register names bit/register definition
BT868/bt869 2.0 internal registers flicker-free video encoder with ultrascale tm technology 2.3 reading information 100123b conexant 2-7 eccf2 0 = disables closed-caption encoding on field 2. 1 = enables closed-caption encoding on field 2. eccf1 0 = disables closed-caption encoding on field 1. 1 = enables closed-caption encoding on field 1. eccgate 0 = normal closed-caption encoding. 1 = enables closed-caption encoding constraints. after encoding, future encoding is disabled until a complete pair of new data bytes is received. this prevents encoding of redundant or incomplete data. ecbar 0 = normal operation 1 = enables color bars. dchroma 0 = normal operation 1 = blank chroma en_out 0 = three-states all outputs. 1 = allows outputs to be enabled (depending upon en_blanko register bit and slave pin). en_blanko enables blank* pin as an output. en_dot enables dot clock synchronization on blank* pin. fieldi 0 = logical 1 on field indicates an even field. 1 = logical 1 on field indicates an odd field. vsynci 0 = active low vsync* 1 = active high vsync* hsynci 0 = active low hsync* 1 = active high hsync* in_mode[2:0] format of pixels at input of encoder: 000 = 24-bit rgb multiplexed 001 = 16-bit rgb multiplexed 010 = 15-bit rgb multiplexed 011 = 24-bit rgb non-multiplexed 100 = 24-bit ycrcb multiplexed 101 = 16-bit ycrcb multiplexed 110 = reserved 111 = 24-bit ycrcb non-multiplexed dis_yflpf luma initial horizontal low pass filter 0 = enable 1 = disable dis_ffilt 0 = enables flickerfilter 1 = disables flickerfilter f_selc[2:0] chroma flickerfilter: 000 = 5 line 001 = 2 line 010 = 3 line 011 = 4 line 100 = alternate 5 line 101 = alternate 5 line 110 = alternate 5 line 111 = alternate 5 line table 2-4. programming detail (4 of 7) bit/register names bit/register definition
2.0 internal registers BT868/bt869 2.3 reading information flicker-free video encoder with ultrascale tm technology 2-8 conexant 100123b f_sely[2:0] luma flickerfilter: 000 = 5 line 001 = 2 line 010 = 3 line 011 = 4 line 100 = alternate 5 line 101 = alternate 5 line 110 = alternate 5 line 111 = alternate 5 line dis_gmushy 0 = enables luma anti-psuedo gamma removal. 1 = disables luma anti-psuedo gamma removal. dis_gmshy 0 = enables luma psuedo gamma removal. 1 = disables luma psuedo gamma removal. ycoring[2:0] luma coring: 000 = bypass 001 = 1/128 of range 010 = 1/64 of range 011 = 1/32 of range 100 = 1/16 of range 101 = 1/8 of range 110 = 1/4 of range 111 = reserved yattenuate[2:0] luma attenuation 000 = 1.0 gain (no attenuation) 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0 gain (force luma to 0) dis_gmushc 0 = enables chroma anti-psuedo gamma removal. 1 =disables chroma anti-psuedo gamma removal. dis_gmshc 0 = enables chroma psuedo gamma removal. 1 = disables chroma psuedo gamma removal. ccoring[2:0] chroma coring: 000 = bypass 001 = 1/128 of range (+/- 1/256 of range) 010 = 1/64 of range (+/- 1/128 of range) 011 = 1/32 of range (+/- 1/64 of range) 100 = 1/16 of range (+/- 1/32 of range) 101 = 1/8 of range (+/- 1/16 of range) 110 = 1/4 of range (+/- 1/8 of range) 111 = reserved table 2-4. programming detail (5 of 7) bit/register names bit/register definition
BT868/bt869 2.0 internal registers flicker-free video encoder with ultrascale tm technology 2.3 reading information 100123b conexant 2-9 cattenuate[2:0] chroma attenuation: 000 = 1.0 gain (no attenuation) 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0 gain (force chroma to 0) out_muxa[1:0] 00 = output video[0] on daca 01 = output video[1] on daca 10 = output video[2] on daca 11 = output video[3] on daca out_muxb[1:0] 00 = output video[0] on dacb 01 = output video[1] on dacb 10 = output video[2] on dacb 11 = output video[3] on dacb out_muxc[1:0] 00 = output video[0] on dacc 01 = output video[1] on dacc 10 = output video[2] on dacc 11 = output video[3] on dacc ccr_start[8:0] closed-captioning clock run-in start in clock cycles from leading edge of hsync* cc_add[11:0] closed-captioning dto increment div2 divides input pixel rate by two (for ccir601 interlaced timing input. mode2x divides selected input clock by two (allows for 2x rather than double-edge clock input). en_async set to 0 for normal operation. out_mode[1:0] 00 = video[0-3] is cvbs/ y/ c/ y_dly 01 = video[0-3] is cvbs_dly/ y/ c/ y_dly 10 = video[0-3] is v/ y/ u/ y_dly 11 = video[0-3] is r/ g/ b/ x (vga mode) lumadly[1:0] this 2-bit value can be used to program the luminance delay in pixels for the cvbs_dly and y_dly output modes. 00 = no delay 01 = 1 pixel 10 = 2 pixels 11 = 3 pixels hsynoffset[9:0] a 2s-complement number. the values range from ? 512 pixels to +511 pixels. this register manip- ulates the falling edge position of the digital hsync output from BT868. the default value is 0 and denotes the standard position of the hsync leading edge. table 2-4. programming detail (6 of 7) bit/register names bit/register definition
2.0 internal registers BT868/bt869 2.3 reading information flicker-free video encoder with ultrascale tm technology 2-10 conexant 100123b vsynoffset[10:0] a 2s-complement number. the values range from ? hclki pixels to +hclki pixels. this register causes the falling edge position of the BT868 ? s digital vsync output to occur earlier ( ? value) or later (+) in time compared to the standard position for ntsc or pal. the default value is 0 and denotes the standard position of the vsync leading edge. hsynwidth[5:0] controls the duration/width of the digital hsync output pulse. value will be hexadecimal and its units are in terms of pixels. a value of 0 is a disallowed condition. the acceptable range is 2 pixels to 3f pixels (=63 decimal). the default value is 2. vsynwidth[2:0] controls the width of the vsync output pulse. denotes the number of lines the vsync digital sig- nal remains low on field transitions. value will be hexadecimal value and its units are in terms of lines. a value of 0 is a disallowed condition. the acceptable range is 1 line to (2 3 ? 1) lines. the default value is 1. datdly delays the falling edge pixel data by 1 full clock period when the falling edge data precedes the ris- ing edge data. ensures that the BT868 moves the falling edge data after the rising edge data. the correct sequence of rising edge data/falling edge data/rising edge data will then be encoded by buteo. the default value for this bit is 0 because most graphics controllers already transmit data in the expected rising edge data/falling edge data sequence. datswp swaps the falling edge pixel data with the rising edge pixel data at the input of the pixel port. the default value for this bit is 0 which tells the vga encoder to expect an order of rising edge data/fall- ing edge data coming from the graphics controller. note(s): vsynwidth, hsynwidth, vsynoffset, and hsynoffset are active only when the BT868/869 is in the master timing mode when the encoder outputs hsync and vsync pulses. in the slave timing mode, these registers are ignored. vsyncwidth and hsyncwidth should never be set to 0. table 2-4. programming detail (7 of 7) bit/register names bit/register definition
100123b conexant 3-1 3 3.0 pc board considerations for optimum performance of the BT868/869, proper cmos layout techniques should be studied in the bt451/457/458 evaluation module operation and measurements application note (an-16), before pc board layout is begun. the layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. the trace length between groups of vaa and gnd pins should be as short as possible to minimize inductive ringing. a well-designed power distribution network is critical to eliminating digital switching noise. the ground plane must provide a low-impedance return path for the digital circuits. a pc board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals, and layers 2 and 3 for ground and power, respectively. 3.1 component placement components should be placed as close as possible to the associated pin in order for traces to be connected point to point. the optimum layout enables the BT868/869 to be located close to the power supply connector and the video output connector. for an illustration, see figure 3-1 . 3.2 power and ground planes for optimum performance, a common digital and analog ground plane and a common digital and analog power plane are recommended. the power plane should provide power to all BT868/869 power pins, reference voltage (vref) circuitry, and comp decoupling. the BT868/869 power plane should be connected to the graphics system power plane (vcc) at a single point through a ferrite bead, as illustrated in figures 3-1 and 3-2 . this bead should be located within 3 inches of the BT868/869. the bead provides resistance to switching currents, acting as a resistor at high frequencies. a low-resistance bead should be used, such as ferroxcube 5659065-3b, fair-rite 2723021447, or tdk bf45-4001. see table 3-1 for a typical parts list for key passive components and figure 3-3 for a schematic diagram of the recommended layout.
3.0 pc board considerations BT868/bt869 3.2 power and ground planes flicker-free video encoder with ultrascale tm technology 3-2 conexant 100123b figure 3-1. power plane illustration BT868 bt decoder analog oscillator 3vaa-BT868 o o vcc3 ferrite bead clocks 5v 3v 3 v o vcc3 data pci or agp connector bracket 4 layer board plane order: signals gnd pwr signals bottom top
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.2 power and ground planes 100123b conexant 3-3 figure 3-2. connection diagram for output filters and other key passive components (1) some modulators may require ac coupling capacitors (10 f). vaa comp vbias vref gnd c7 c8 c2 ? c6 fsadjust rset = daca dacb dacc BT868/869 power plane p p p lpf lpf to v i d e o connector ground (power supply connector) +3.3 v (vcc) vaa schottky diodes schottky diodes rf modulator/cvbs out 75 trap rf modulator lpf 22 pf 1.8 h 270 pf BT868/869 c10 + c1 l1 rf mod/cvbs rf 330 pf gnd to filter dac output 22 pf 1.8 h 270 pf 330 pf audio 82 zin = 1 k 75 ?, 75 ?, 75 ?, (1) p cvbs c9 buffer 100 ? ,1% 1% 1% 1% table 3-1. typical parts list for key passive components location description vendor part number c1 ? c9 0.1 f ceramic capacitor erie rpe112z5u104m50v c10 47 f capacitor mallory csr13f476km l1 ferrite bead ? surface mount fair-rite 2743021447 rset 1% metal film resistor dale cmf-55c trap ceramic resonator murata tpsx.xmj or mb2 (where x.x = sound carrier frequency in mhz) schottky diodes bat85 (bat54f dual) hp 5082-2305 (1n6263) siemens bat 64-04 (dual) note(s): vendor numbers are listed only as a guide. substitution of devices with similar characteristics will not affect BT868/869 performance.
3.0 pc board considerations BT868/bt869 3.2 power and ground planes flicker-free video encoder with ultrascale tm technology 3-4 conexant 100123b figure 3-3. complete BT868/bt869 recommended layout
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.3 decoupling 100123b conexant 3-5 3.3 decoupling 3.3.1 device decoupling for optimum performance, all capacitors should be located as close as possible to the device, and the shortest possible leads (consistent with reliable operation) should be used to reduce the lead inductance. chip capacitors are recommended for minimum lead inductance. radial lead ceramic capacitors can be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. values are chosen to have self-resonance above the pixel clock. 3.3.2 power supply decoupling the best power supply performance is obtained with a 0.1 f ceramic capacitor decoupling each group of vaa pins and each group of vdd pins to gnd. the capacitors should be placed as close as possible to the device vaa/vdd pins and gnd pins and connected with short, wide traces. the 47 f capacitor shown in figure 3-2 is for low-frequency power supply ripple; the 0.1 f capacitors are for high-frequency power supply noise rejection. when a linear regulator is used, the proper power-up sequence must be verified to prevent latchup. a linear regulator is recommended to filter the analog power supply if the power supply noise is greater than or equal to 200 mv. this is especially important when a switching power supply is used, and the switching frequency is close to the raster scan frequency. about 5% of the power supply hum and ripple noise less than 1 mhz will couple onto the analog outputs. 3.3.3 comp decoupling the comp pin must be decoupled to the closest vaa pin, typically with a 0.1 f ceramic capacitor. low-frequency supply noise will require a larger value. the comp capacitor must be as close as possible to the comp and vaa pins. a surface-mount ceramic chip capacitor is preferred for minimal lead inductance. lead inductance degrades the noise rejection of the circuit. short, wide traces will also reduce lead inductance. 3.3.4 vref decoupling a 0.1 f ceramic capacitor should be used to decouple this input to gnd. 3.3.5 vbias decoupling a 0.1 f ceramic capacitor should be used to decouple this output to gnd.
3.0 pc board considerations BT868/bt869 3.4 signal interconnect flicker-free video encoder with ultrascale tm technology 3-6 conexant 100123b 3.4 signal interconnect 3.4.1 digital signal interconnect the digital inputs to the BT868/869 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane or analog output signals. most of the noise on the analog outputs will be caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. the digital edge rates should not be faster than necessary, as feedthrough noise is proportional to the digital edge rates. lower-speed applications will benefit from using lower-speed logic (3 ? 5 ns edge rates) to reduce data-related noise on the analog outputs. transmission lines will mismatch if the lines do not match the source and destination impedance. this will degrade signal fidelity if the line length reflection time is greater than one-fourth the signal edge time (refer to application notes an-11 and an-12). line termination or line-length reduction is the solution. for example, logic edge rates of 2 ns require line lengths of less than 4 inches without use of termination. ringing can be reduced by damping the line with a series resistor (30 ? 300 ? ). radiation of digital signals can also be picked up by the analog circuitry. this is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with damping resistors, and minimizing coupling through pc board capacitance by routing the digital signals at a 90-degree angle to any analog signals. the clock driver and all other digital devices must be adequately decoupled to prevent noise generated by the digital devices from coupling into the analog circuitry. 3.4.2 analog signal interconnect the BT868/869 should be located as close as possible to the output connectors to minimize noise pickup and reflections caused by impedance mismatch. the analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces. to maximize the high-frequency power supply rejection, the video output signals should overlay the ground plane. for maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. the load resistor connection between the video outputs and gnd should be as close as possible to the BT868/869 to minimize reflections. unused analog outputs should be connected to gnd.
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.5 applications information 100123b conexant 3-7 3.5 applications information 3.5.1 electrostatic discharge and latchup considerations correct electrostatic discharge (esd)-sensitive handling procedures are required to prevent device damage. device damage can produce symptoms of catastrophic failure or erratic device behavior with leaky inputs. all logic inputs should be held low until power to the device has settled to the specified tolerance. dac power decoupling networks with large time constants should be avoided; they could delay vaa and vdd power to the device. ferrite beads must be used only for analog power vaa decoupling. inductors cause a time-constant delay that induces latchup, and should not be substituted for a ferrite bead. latchup can be prevented by ensuring that all vaa and all gnd pins are at the same potential and that the vaa and vdd supply voltage is applied before the signal pin voltages. the correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage. 3.5.2 clock and subcarrier stability the color subcarrier is derived directly from the clko (derived from xtalin/xtalout) clki when en_xclk=1 input, hence any jitter or frequency deviation of clko (xtalin/xtalout) or clki when en_xclk=1 will be transferred directly to the color subcarrier. jitter within the valid clko cycle interval will result in hue noise on the color subcarrier on the order of 0.9 ? 1.6 degrees per nanosecond. random hue noise can result in degradation in am/pm noise ratio (typically around 40 db for consumer media such as videodiscs and vcrs). periodic or coherent hue noise can result in differential phase error (which is limited to 10 degrees by fcc cable tv standards). any frequency deviation of clko from nominal will challenge the subcarrier tracking capability of the destination receiver. this may range from a few parts-per-million (ppm) for broadcast equipment to 100 ppm for industrial equipment, to a few hundred ppm for consumer equipment. greater subcarrier tracking range generally results in poorer subcarrier decoding dynamic range, so that receivers that tolerate jitter and wide subcarrier frequency deviation will introduce more noise in the decoded image. crystal-based clock sources with a maximum total deviation of 50 ppm (ntsc) or 25 ppm (pal) across the temperature range of 0 c to 70 c produce the best results for consumer and industrial applications. in rare cases, temperature-compensated clock sources with tighter tolerances may be warranted for broadcast or more stringent pal (e.g., type i) applications. some applications call for maintaining correct subcarrier-horizontal (sc-h) phasing for correct color framing. this requires subcarrier coherence within specified tolerances over a four-field interval for 525-line systems or 8 fields for 625-line systems. any clock interruption (even during vertical blanking interval) which results in mis-registration of the clki input or nonstandard pixel counts per line, can result in sc-h excursions outside the ntsc limit of 40 degrees
3.0 pc board considerations BT868/bt869 3.5 applications information flicker-free video encoder with ultrascale tm technology 3-8 conexant 100123b (reference eia rs170a) or the pal limit of 20 degrees (reference ebu d23-1984). in slave mode, any deviation exceeding the 50 ppm (ntsc) or 25 ppm (pal) limits of the number clko cycles between hsync* falling edges when in slave mode may result in a switch to master mode. 3.5.3 filtering radio frequency modulator connection the BT868/869 ? s internal upsampling filter alleviates external filtering requirements by moving significant sampling alias components above 19 mhz and reducing the sinx/x aperture loss up to the filters passband cutoff of 5.75 mhz. while typical chrominance subcarrier decoders can handle the BT868/869 output signals without analog filtering, the higher frequency alias products pose some emi concerns and may create troublesome images when introduced to a radio frequency (rf) modulator. when the video is presented to an rf modulator, it should be free of energy in the region of the aural subcarrier (4.5 mhz for ntsc, 5.5 ? 6.5 mhz for pal). hence some additional frequency traps may be necessary when the video signal contains fundamental or harmonic energy (as from unfiltered character generators) in that region. where better frequency response flatness is required, some peaking in the analog filter is appropriate to compensate for residual digital filter losses with sufficient margin to tolerate 10% reactive components. a three-pole elliptic filter (one inductor, three capacitors) with a 6.75 mhz passband can provide at least 45 db attenuation (including sinx/x loss) of frequency components above 20 mhz and provide some flexibility for mild peaking or special traps. an inductor value with a self-resonant frequency above 80 mhz is chosen so that its intrinsic capacitance contributes less than 10% of the total effective circuit value. the inductor itself may induce 1% (0.1 db) loss. any additional ferrites introduced for emi control should have less than 5 ? impedance below 5 mhz to minimize additional losses. the capacitor to ground at the BT868/869 output pin is compensating for the parasitic capacitance of the chip plus any protection diodes and lumped circuit traces (about 22 pf + 5 pf/diode). some filter peaking can be accomplished by splitting the 75 ? source impedance across the reactive pi filter network. however, this will also introduce some chrominance-luminance delay distortion in the range of 10 ? 20 ns for a maximum of 0.5 db boost at the subcarrier frequency. the filter network feeding an rf modulator may include the aforementioned trap, which could take two forms depending on the depth of attenuation and type of resonator device employed. the trap circuitry can interact with the lowpass filter, compromising frequency response flatness. a simple pnp buffer can preserve the benefits of an oversampling encoder when simultaneous composite video baseband signals (cvbs) are required for driving external cables. in addition, an active video buffer, serves to isolate the rf modulator signal amplitude from anomalies in the external termination. this buffer can be implemented with a transistor array or video amplify ic which provides a gain of two (before series termination), capable of driving 740 a into the 75 ? destination, and is biased within its input/output compliance range. when simultaneous y/c (s-video) outputs are not required, a second cvbs signal can be created (with a 600 mv sync to tip offset) by tying these pins together with a single termination resistor (typically 75 ? ) and driving the lowpass filter circuit.
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.6 BT868/bt869 evaluation board 100123b conexant 3-9 the rf modulator typically has a high input impedance (about 1k ? 30%) and loose tolerance. consequently, the amplitude variation at the modulator input will be greater, especially when the trap is properly terminated at the modulator input for maximum effect. some modulators, video or aural fidelity, degrade dramatically when overdriven, so the value of the effective termination (nominally 37.5 ? ) may need to be adjusted downward to maintain sufficient linearity (or depth of modulation margin) in the rf signal. a two-section trap (with associated inductor) may be warranted to achieve better than 20 db attenuation when stereo, sap, or am aural carriers are generated, or when > 40 db audio dynamic range is desired. some impedance isolation (e.g., buffer) may be required before the trap to obtain the flattest frequency response. see figure 3-2 . 3.6 BT868/bt869 evaluation board see figure 3-4 for a schematic diagram of the BT868 evk evaluation card. this is a reference design intended to facilitate implementation of conexant ? s vga encoder into a graphics card. the BT868evk may be obtained through your local conexant semiconductor sales office.
3.0 pc board considerations BT868/bt869 3.6 BT868/bt869 evaluation board flicker-free video encoder with ultrascale tm technology 3-10 conexant 100123b figure 3-4. BT868/bt869 evaluation board (1 of 6)
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.6 BT868/bt869 evaluation board 100123b conexant 3-11 figure 3-4. BT868/bt869 evaluation board (2 of 6)
3.0 pc board considerations BT868/bt869 3.6 BT868/bt869 evaluation board flicker-free video encoder with ultrascale tm technology 3-12 conexant 100123b figure 3-4. BT868/bt869 evaluation board (3 of 6)
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.6 BT868/bt869 evaluation board 100123b conexant 3-13 figure 3-4. BT868/bt869 evaluation board (4 of 6)
3.0 pc board considerations BT868/bt869 3.6 BT868/bt869 evaluation board flicker-free video encoder with ultrascale tm technology 3-14 conexant 100123b figure 3-4. BT868/bt869 evaluation board (5 of 6)
BT868/bt869 3.0 pc board considerations flicker-free video encoder with ultrascale tm technology 3.6 BT868/bt869 evaluation board 100123b conexant 3-15 figure 3-4. BT868/bt869 evaluation board (6 of 6)
3.0 pc board considerations BT868/bt869 3.7 serial interface flicker-free video encoder with ultrascale tm technology 3-16 conexant 100123b 3.7 serial interface 3.7.1 data transfer on the serial interface bus figure 3-5 illustrates the relationship between sid (serial interface data) and sic (serial interface clock) to be used when programming the internal registers via the serial interface bus. if the bus is not being used, both sid and sic lines must be left high. every byte put onto the sid line should be 8 bits long (msb first), followed by an acknowledge bit, which is generated by the receiving device. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always the slave address byte. if this is the device ? s own address, the device will generate an acknowledge by pulling the sid line low during the ninth clock pulse, then accept the data in subsequent bytes (auto-incrementing the subaddress) until another stop condition is detected. the eighth bit of the address byte is the read/write bit (high = read from addressed device; low = write to the addressed device) so, for the BT868/869, the subaddress is only considered valid if the r/w bit is low. data bytes are always acknowledged during the ninth clock pulse by the addressed device. note that during the acknowledge period, the transmitting device must leave the sid line high. premature termination of the data transfer is allowed by generating a stop condition at any time. when this happens, the BT868/869 will remain in the state defined by the last complete data byte transmitted and any master acknowledge subsequent to reading the chip id (subaddress 0x89) is ignored. figure 3-5. sid/sic diagram (1) acknowledge generated by BT868/869. 1 sic 23456789 123456789 123456 789 subsequent bytes and acknowledge interpreted as data values for auto-incrementing subaddress locations sid msb lsb (1) start condition stop condition subaddress (xx) data (xx) main address (xx) (1) (1) slave
100123b conexant 4-1 4 4.0 parametric information 4.1 dc electrical parameters dc electrical parameters are defined in tables 4-1 through 4-3 . ac electrical parameters are defined in table 4-4 . timing diagrams are in figures 4-1 through 4-3 . table 4-1. recommended operating conditions parameter symbol min typ max units power supply vaa, vdd 3.00 3.30 3.60 v serial input supply vdd_si 3.00 5.25 v ambient operating temperature ta 0 70 c dac output load rl 37.5 w nominal rset rset 100.0 w table 4-2. absolute maximum rating (1 of 2) parameter symbol min typ max units vaa, vdd (measured to gnd) 7.0 v vdd_si (measured to gnd) 7.0 v
4.0 parametric information BT868/bt869 4.1 dc electrical parameters flicker-free video encoder with ultrascale tm technology 4-2 conexant 100123b voltage on any signal pin (1) gnd ? 0.5 vdd_si+ 0.5 v analog output short circuit duration to any power supply or common isc indefinite storage temperature ts ? 65 +150 c junction temperature tj +125 c vapor phase soldering (1 minute) tvsol 220 c (1) this device employs high-impedance cmos devices on all signal pins. it should be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 v can cause destructive latchup. stresses above those listed under ? absolute maximum ratings ? can cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods can affect device reliability. table 4-2. absolute maximum rating (2 of 2) parameter symbol min typ max units table 4-3. dc characteristics (1 of 2) parameter symbol min typ max units video d/a resolution 10 10 10 bits output current-dac code 1023 (iout full scale) 34.13 ma output voltage-dac code 1023 1.28 v video level error (nominal resistors) 5 % output capacitance (of dac output) 22 pf digital inputs (except those specified below) input high voltage vih 2.0 vdd_i + 0.5 v input low voltage vil gnd ? 0.5 0.8 v input high current (vin = 2.4 v) iih 1 a input low current (vin = 0.4 v) iil ? 1a input capacitance (f =1 mhz, vin = 2.4 v) cin 7 pf sid, sdo input high voltage vih 0.7 * vdd_si vdd_si + 0.5 v input low voltage vil gnd ? 0.5 0.3 * vdd_si v clki input input high voltage vih 2.4 vdd_i + 0.5 v input low voltage vil gnd ? 0.5 0.8 v
BT868/bt869 4.0 parametric information flicker-free video encoder with ultrascale tm technology 4.1 dc electrical parameters 100123b conexant 4-3 digital outputs output high voltage (ioh = ? 400 a) voh 2.4 vdd v output low voltage (iol = 3.2 ma) vol gnd 0.4 v three-state current ioz 50 a output capacitance cdout 10 pf note(s): recommended operating conditions, ntsc ccir 601 operation, and internal clock frequency = 27 mhz. as the above parameters are guaranteed over the full temperature range (0 c to 70 c), temperature coefficients are not specified or required. typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 v. table 4-3. dc characteristics (2 of 2) parameter symbol min typ max units
4.0 parametric information BT868/bt869 4.2 ac electrical parameters flicker-free video encoder with ultrascale tm technology 4-4 conexant 100123b 4.2 ac electrical parameters table 4-4. ac characteristics (1 of 2) parameter eia/tia 250c ref ccir 567 symbol min typ max units hue accurac (1, 2) color saturation accuracy (1, 2) % chroma am/pm noise (3) 1 mhz red field db rms differential gain (2) 6.2.2.1 c3.4.1.3 % p ? p differential phase (2) 6.2.2.2 c3.4.1.4 p ? p snr (unweighted 100 ire y ramp tilt correct) (2) rms 6.3.1 db rms peak periodic 6.3.2 db p ? p 100 ire multiburst (3) 6.1.1 ire gain/frequency c3.5.4.1 chroma/luma gain ineq (3) 6.1.2.2 c3.5.3.1 ire chroma/luma delay ineq (3) 6.1.2 c3.5.3.2 ns short time distortion 100 ire/pixel (3) 6.1.6 % luminance nonlinearity (2) 6.2.1 % chroma/luma intermod (2) 6.2.3 ire chroma nonlinear gain (2) 6.2.4.1 ire chroma nonlinear phase (2) 6.2.4.2 pixel/control setup time (2) 13 12 ns pixel/control hold time (2) 2 .35 ns control output delay time (4) 315ns control output hold time (4) 42 ns clki/o frequency 40.5 mhz clki/o pulse width low duty cycle 40 50 60 % clki/o pulse width high duty cycle 40 50 60 %
BT868/bt869 4.0 parametric information flicker-free video encoder with ultrascale tm technology 4.2 ac electrical parameters 100123b conexant 4-5 clko to clki delay 7 0.8 clko cycles slave to hsync*/vsync* three-state 5 2 clki cycles slave to hsync*/vsync* active 6 2 clki cycles vaa supply current 132 ma vaa power-down current 1 ma vdd supply current 118 ma vdd power-down current 1 ma total supply current 250 ma (1) 5/7.5/75/7.5 color bars normalized to burst. (2) guaranteed by characterization. (3) without post filter. guaranteed by design. (4) control pins are defined as: p[11:0], blank*, hsync*, vsync*, field, clkdir, reset*, pal, and slave. 5. ? recommended operating conditions, ? ntsc ccir 601 operation, and clk frequency = 27 mhz. analog output load < 75 pf. hsync*, vsync*, blank*, and field output load < 75 pf. as the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 v. video input and output timing is shown in figure 4-1 . table 4-4. ac characteristics (2 of 2) parameter eia/tia 250c ref ccir 567 symbol min typ max units
4.0 parametric information BT868/bt869 4.2 ac electrical parameters flicker-free video encoder with ultrascale tm technology 4-6 conexant 100123b figure 4-1. interface timing clki p[11:0] hsync*,vsync* 1 2 3 4 .8 2.4 blank* (output) hsync*,vsync*, blank* (input) 5 slave 1 2 1 2 hsync*,vsync* 6 clko/clki (internal/external clock source) clko 7
BT868/bt869 4.0 parametric information flicker-free video encoder with ultrascale tm technology 4.2 ac electrical parameters 100123b conexant 4-7 figure 4-2. master mode with flicker filter interface timing internal sample vsync* (output) clki hsync* (output) p[11:0] blank* (input) blank* (output) (mux mode) p[23:0] (non- clko internal line h_blanki - 3 mux mode) counter counter sample h_blank sample h_blank sample h_blank sample h_blank sample1 sample2 sample2 sample1 line 1 line v_blank1+1 pol poh p1l p1h p2l pnh p0 p1 p2 pn p2h
4.0 parametric information BT868/bt869 4.2 ac electrical parameters flicker-free video encoder with ultrascale tm technology 4-8 conexant 100123b figure 4-3. slave mode with flicker filter interface timing clko clki vsync* (input) hsync* (input) blank* (input) blank* (output) internal sample h_blank pol poh p1l p1h p2l pnl pnh p0 p1 p2 pn sample h_blank sample1 sample hclki sample h_blanki -2 sample h_blanki sample h_blanki -1 counter
BT868/bt869 4.0 parametric information flicker-free video encoder with ultrascale tm technology 4.3 mechanical drawing 100123b conexant 4-9 4.3 mechanical drawing a detailed mechanical diagram is shown in figure 0-1 . figure 0-1. 80 mqfp package diagram d d2 e d1 e1 e2 b a l a2 a1 e 1.60 (.063) ref. top view bottom view side view detail a 80 mqfp - 1.6/0.15mm form s y m b o l all dimensions in millimeters min. nom. max. a a1 a2 d d1 d2 e e1 e2 l l1 e b --- 0.05 16.95 16.95 0.73 0.25 --- --- 2.0 ref. --- 14.0 ref. 12.35 ref. --- 14.0 ref. 12.35 ref. 0.80 16 ref. 0.65 bsc --- 2.4 0.35 17.45 17.45 1.03 0.45
4.0 parametric information BT868/bt869 4.3 mechanical drawing flicker-free video encoder with ultrascale tm technology 4-10 conexant 100123b
100123b conexant a-1 a appendix a. scaling and i/o timing register calculations the calculated values are used to program the registers controlling the total active pixels and lines in the input frame and the output field, as well as the vertical scaling register and the clock pll registers. these calculations assume pixel resolution for synchronizing the graphics controller, and master mode operation unless otherwise stated, and require the following input values: mfp ? minimum front porch blanking in the input in clocks = max (12, controller_minimum_front_porch_blanking_clocks); mbp ? minimum back porch blanking in the input in clocks = max (4, controller_minimum_back_porch_blanking_clocks); voc ? desired vertical overscan compensation (e.g., 0.15) hoc ? desired horizontal overscan compensation (e.g., 0.15) v_activei ? active lines per input frame (e.g., 480 or 600) h_active ? active pixels per input line (e.g., 640 or 800) alo ? target active lines per output field (see table a-2 ) tlo ? total lines per output field (see table a-2 ) ato ? active time per output line (see table a-2 ) tto ? total time per output line (see table a-2 ) table a-1 displays details of the video formats. table a-2 details the constant values dependent on encoding modes. figures a-1 through a-4 diagram overscan compensation. tables a-3 through a-10 display overscan values. table a-1. video formats mode ntsc ntsc- 60hz pal- bdghi pal-n pal-nc pal-m pal-m60hz pal-60 fsc (hz) 3,579,545 3,579,545 4,433,618.75 4,433,618.75 3,582,056.25 3,575,611.88 3,575,611.88 4,433,619.49 burst start 5.3 s5.3 s5.60 s5.60 s5.60 s5.80 s5.80 s5.60 s burst end 7.82 s7.82 s7.85 s7.85 s8.11 s8.32 s8.32 s7.85 s hsync width 4.70 s4.70 s4.70 s4.70 s4.70 s4.70 s4.70 s4.70 s hsync frequency 63.555 s64 s64 s64 s64 s 63.555 s64 s64 s active begin 9.40 s9.40 s 10.5 s9.40 s 10.5 s9.40 s9.40 s 10.5 s image center 35.667 s 35.667 s 36.407 s 35.667 s 36.407 s 35.667 s 35.667 s 36.407 s front porch 1.50 s1.50 s1.50 s1.50 s1.50 s1.50 s1.50 s1.50 s
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-2 conexant 100123b table a-2. constant values dependent on encoding mode modes interlaced non-interlaced pal ntsc pal ntsc alo 288 243 288 243 tlo 312.5 262.5 312 262 ato 52.0 s 52.65556 s52.0 s 52.65556 s tto 64.0 s 63.55556 s64.0 s 63.55556 s figure a-1. overscan compensation, 640x480 ntsc, 20 clock hblank 8 10 12 14 16 18 20 22 8 10 12 14 16 18 20 22 vertical overscan compensation percentage horizontal overscan compensation percentage overscan compensation pecentage pairs for 640x480 ntsc w/ character clock 1 +, 8 *, 9 o
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-3 figure a-2. overscan compensation, 640x480 pal, 20 clock hblank 8 10 12 14 16 18 20 22 8 10 12 14 16 18 20 22 24 vertical overscan compensation percentage horizontal overscan compensation percentage overscan compensation pecentage pairs for 640x480 pal w/ character clock 1 +, 8 *, 9 o
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-4 conexant 100123b figure a-3. overscan compensation, 800x600 ntsc 8 10 12 14 16 18 20 22 8 10 12 14 16 18 20 22 24 vertical overscan compensation percentage horizontal overscan compensation percentage overscan compensation percentage pairs for 800x600 ntsc w/ character clock 1 +, 8 *, 9 o 0 us horizontal blanking 1 us 2 us 3 us .75 us
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-5 figure a-4. overscan compensation, 800x600 pal 8 10 12 14 16 18 20 22 8 10 12 14 16 18 20 22 vertical overscan compensation percentage horizontal overscan compensation percentage overscan compensation pecentage pairs for 800x600 pal w/ character clock 1 +, 8 *, 9 o table a-3. overscan values, 640x480 ntsc, 1 pixel resolution, 2.5 s hblank (1 of 3) controller pixels encoder pixels overscan (percent) total active total h_clki v_linesi v_activeo h_clko h v delta 780 665 190 988 21.81 21.81 0.00 780 595 212 884 12.61 12.76 ? 0.14 784 600 210 896 13.79 13.58 0.21 780 630 200 936 17.47 17.70 ? 0.23 777 575 220 851 9.23 9.47 ? 0.24 785 630 200 942 18.00 17.70 0.30 777 625 202 925 16.49 16.87 ? 0.38 777 650 194 962 19.70 20.16 ? 0.46 775 588 215 868 11.00 11.52 ? 0.52 775 651 194 961 19.62 20.16 ? 0.55
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-6 conexant 100123b 777 600 210 888 13.01 13.58 ? 0.57 775 609 207 899 14.07 14.81 ? 0.74 775 630 200 930 16.94 17.70 ? 0.76 790 630 200 948 18.51 17.70 0.82 791 600 210 904 14.55 13.58 0.97 770 645 196 946 18.34 19.34 ? 1.00 770 585 216 858 9.97 11.11 ? 1.14 770 660 191 968 20.20 21.40 ? 1.20 770 615 205 902 14.36 15.64 ? 1.28 770 630 200 924 16.40 17.70 ? 1.30 795 630 200 954 19.03 17.70 1.33 770 600 210 880 12.22 13.58 ? 1.36 795 595 212 901 14.26 12.76 1.51 765 665 190 969 20.28 21.81 ? 1.53 798 650 194 988 21.81 20.16 1.65 798 600 210 912 15.30 13.58 1.72 798 625 202 950 18.69 16.87 1.81 800 630 200 960 19.53 17.70 1.84 765 630 200 918 15.85 17.70 ? 1.84 765 595 212 867 10.90 12.76 ? 1.86 800 609 207 928 16.76 14.81 1.94 798 575 220 874 11.62 9.47 2.15 763 600 210 872 11.41 13.58 ? 2.17 800 588 215 896 13.79 11.52 2.26 805 630 200 966 20.03 17.70 2.34 760 630 200 912 15.30 17.70 ? 2.40 805 615 205 943 18.08 15.64 2.44 805 600 210 920 16.03 13.58 2.45 805 645 196 989 21.89 19.34 2.55 756 650 194 936 17.47 20.16 ? 2.69 table a-3. overscan values, 640x480 ntsc, 1 pixel resolution, 2.5 s hblank (2 of 3) controller pixels encoder pixels overscan (percent) total active total h_clki v_linesi v_activeo h_clko h v delta
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-7 756 625 202 900 14.17 16.87 ? 2.70 805 585 216 897 13.88 11.11 2.77 810 630 200 972 20.53 17.70 2.83 755 630 200 906 14.74 17.70 ? 2.96 805 570 222 874 11.62 8.64 2.97 756 600 210 864 10.59 13.58 ? 2.99 table a-3. overscan values, 640x480 ntsc, 1 pixel resolution, 2.5 s hblank (3 of 3) controller pixels encoder pixels overscan (percent) total active total h_clki v_linesi v_activeo h_clko h v delta table a-4. overscan values, 640x480 ntsc, 8 pixel resolution, 2.5 s hblank controller pixels encoder pixels overscan (percent) total active total h_clki v_linesi v_activeo h_clko h v delta 784 600 210 896 13.79 13.58 0.21 800 630 200 960 19.53 17.70 1.84 800 609 207 928 16.76 14.81 1.94 800 588 215 896 13.79 11.52 2.26 760 630 200 912 15.30 17.70 ? 2.40 840 615 205 984 21.50 15.64 5.86 840 600 210 960 19.53 13.58 5.95 840 610 207 976 20.85 14.81 6.04 840 595 212 952 18.86 12.76 6.10 840 605 209 968 20.20 13.99 6.21 840 590 214 944 18.17 11.93 6.23 840 585 216 936 17.47 11.11 6.36 840 580 218 928 16.76 10.29 6.47 720 665 190 912 15.30 21.81 ? 6.51 840 575 220 920 16.03 9.47 6.57 840 570 222 912 15.30 8.64 6.66 720 630 200 864 10.59 17.70 ? 7.10
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-8 conexant 100123b table a-5. overscan values, 640x480 ntsc, 9 pixel resolution, 2.5 s hblank controller pixels encoder pixels overscan (percent) total active total h v v h h v delta 765 665 190 969 20.28 21.81 ? 1.53 765 630 200 918 15.85 17.70 ? 1.84 765 595 212 867 10.90 12.76 ? 1.86 756 650 194 936 17.47 20.16 ? 2.69 756 625 202 900 14.17 16.87 ? 2.70 810 630 200 972 20.53 17.70 2.83 756 600 210 864 10.59 13.58 ? 2.99 810 595 212 918 15.85 12.76 3.09 819 600 210 936 17.47 13.58 3.89 819 625 202 975 20.77 16.87 3.90 819 575 220 897 13.88 9.47 4.42 720 665 190 912 15.30 21.81 ? 6.51 720 630 200 864 10.59 17.70 ? 7.10 855 595 212 969 20.28 12.76 7.52 693 650 194 858 9.97 20.16 ? 10.20 882 575 220 966 20.03 9.47 10.57 900 574 220 984 21.50 9.47 12.03 675 665 190 855 9.65 21.81 ? 12.16 table a-6. overscan values, 640x480 pal, 1 pixel resolution, 2.5 s hblank (1 of 4) controller pixels encoder pixels overscan (percent) total active total h v v h h v delta 945 625 240 945 16.65 16.67 ? 0.02 946 625 240 946 16.73 16.67 0.07 944 625 240 944 16.56 16.67 ? 0.11 947 625 240 947 16.82 16.67 0.16 943 625 240 943 16.47 16.67 ? 0.20 948 625 240 948 16.91 16.67 0.24 942 625 240 942 16.38 16.67 ? 0.29 949 625 240 949 17.00 16.67 0.33
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-9 941 625 240 941 16.29 16.67 ? 0.37 950 625 240 950 17.09 16.67 0.42 950 600 250 912 13.63 13.19 0.44 940 625 240 940 16.20 16.67 ? 0.46 950 650 231 988 20.27 19.79 0.48 950 575 261 874 9.88 9.38 0.50 951 625 240 951 17.17 16.67 0.51 939 625 240 939 16.11 16.67 ? 0.55 952 625 240 952 17.26 16.67 0.59 938 625 240 938 16.02 16.67 ? 0.64 953 625 240 953 17.35 16.67 0.68 937 625 240 937 15.93 16.67 ? 0.73 954 625 240 954 17.43 16.67 0.77 936 625 240 936 15.84 16.67 ? 0.82 955 625 240 955 17.52 16.67 0.85 935 625 240 935 15.75 16.67 ? 0.91 956 625 240 956 17.61 16.67 0.94 934 625 240 934 15.66 16.67 ? 1.00 957 625 240 957 17.69 16.67 1.02 933 625 240 933 15.57 16.67 ? 1.09 958 625 240 958 17.78 16.67 1.11 932 625 240 932 15.48 16.67 ? 1.18 959 625 240 959 17.86 16.67 1.20 931 625 240 931 15.39 16.67 ? 1.27 960 625 240 960 17.95 16.67 1.28 930 625 240 930 15.30 16.67 ? 1.36 961 625 240 961 18.03 16.67 1.37 962 625 240 962 18.12 16.67 1.45 929 625 240 929 15.21 16.67 ? 1.46 963 625 240 963 18.20 16.67 1.54 928 625 240 928 15.12 16.67 ? 1.55 964 625 240 964 18.29 16.67 1.62 table a-6. overscan values, 640x480 pal, 1 pixel resolution, 2.5 s hblank (2 of 4) controller pixels encoder pixels overscan (percent) total active total h v v h h v delta
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-10 conexant 100123b 927 625 240 927 15.03 16.67 ? 1.64 925 650 231 962 18.12 19.79 ? 1.67 965 625 240 965 18.37 16.67 1.71 926 625 240 926 14.94 16.67 ? 1.73 966 625 240 966 18.46 16.67 1.79 925 625 240 925 14.84 16.67 ? 1.82 967 625 240 967 18.54 16.67 1.88 925 600 250 888 11.30 13.19 ? 1.90 924 625 240 924 14.75 16.67 ? 1.91 968 625 240 968 18.63 16.67 1.96 923 625 240 923 14.66 16.67 ? 2.01 969 625 240 969 18.71 16.67 2.04 922 625 240 922 14.57 16.67 ? 2.10 970 625 240 970 18.79 16.67 2.13 921 625 240 921 14.47 16.67 ? 2.19 971 625 240 971 18.88 16.67 2.21 920 625 240 920 14.38 16.67 ? 2.29 972 625 240 972 18.96 16.67 2.30 973 625 240 973 19.04 16.67 2.38 919 625 240 919 14.29 16.67 ? 2.38 974 625 240 974 19.13 16.67 2.46 918 625 240 918 14.19 16.67 ? 2.47 975 625 240 975 19.21 16.67 2.54 917 625 240 917 14.10 16.67 ? 2.57 976 625 240 976 19.29 16.67 2.63 975 600 250 936 15.84 13.19 2.65 916 625 240 916 14.01 16.67 ? 2.66 977 625 240 977 19.38 16.67 2.71 915 625 240 915 13.91 16.67 ? 2.75 table a-6. overscan values, 640x480 pal, 1 pixel resolution, 2.5 s hblank (3 of 4) controller pixels encoder pixels overscan (percent) total active total h v v h h v delta
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-11 978 625 240 978 19.46 16.67 2.79 975 575 261 897 12.19 9.38 2.81 914 625 240 914 13.82 16.67 ? 2.85 979 625 240 979 19.54 16.67 2.87 913 625 240 913 13.72 16.67 ? 2.94 980 625 240 980 19.62 16.67 2.96 table a-6. overscan values, 640x480 pal, 1 pixel resolution, 2.5 s hblank (4 of 4) controller pixels encoder pixels overscan (percent) total active total h v v h h v delta table a-7. overscan values, 640x480 pal, 8 pixel resolution, 2.5 s hblank (1 of 2) controller pixels encoder pixels overscan (percent) total active total h v v h h v delta 944 625 240 944 16.56 16.67 ? 0.11 952 625 240 952 17.26 16.67 0.59 936 625 240 936 15.84 16.67 ? 0.82 960 625 240 960 17.95 16.67 1.28 928 625 240 928 15.12 16.67 ? 1.55 968 625 240 968 18.63 16.67 1.96 920 625 240 920 14.38 16.67 ? 2.29 976 625 240 976 19.29 16.67 2.63 912 625 240 912 13.63 16.67 ? 3.04 984 625 240 984 19.95 16.67 3.28 904 625 240 904 12.87 16.67 ? 3.80 992 625 240 992 20.60 16.67 3.93 1000 625 240 1000 21.23 16.67 4.56 896 625 240 896 12.09 16.67 ? 4.58 1000 620 242 992 20.60 15.97 4.62 1000 615 244 984 19.95 15.28 4.67 1000 610 246 976 19.29 14.58 4.71 1000 605 248 968 18.63 13.89 4.74 1000 600 250 960 17.95 13.19 4.75 1000 630 239 1008 21.86 17.01 4.84 1000 575 261 920 14.38 9.38 5.01
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-12 conexant 100123b 1000 580 259 928 15.12 10.07 5.05 1000 585 257 936 15.84 10.76 5.08 1000 590 255 944 16.56 11.46 5.10 1000 595 253 952 17.26 12.15 5.11 1008 625 240 1008 21.86 16.67 5.19 888 625 240 888 11.30 16.67 ? 5.37 880 625 240 880 10.49 16.67 ? 6.18 872 625 240 872 9.67 16.67 ? 7.00 table a-7. overscan values, 640x480 pal, 8 pixel resolution, 2.5 s hblank (2 of 2) controller pixels encoder pixels overscan (percent) total active total h v v h h v delta table a-8. overscan values, 640x480 pal, 9 pixel resolution, 2.5 s hblank controller pixels encoder pixels overscan (percent) total active total h v v h h v delta 945 625 240 945 16.65 16.67 ? 0.02 954 625 240 954 17.43 16.67 0.77 936 625 240 936 15.84 16.67 ? 0.82 963 625 240 963 18.20 16.67 1.54 927 625 240 927 15.03 16.67 ? 1.64 972 625 240 972 18.96 16.67 2.30 918 625 240 918 14.19 16.67 ? 2.47 981 625 240 981 19.71 16.67 3.04 909 625 240 909 13.35 16.67 ? 3.32 990 625 240 990 20.44 16.67 3.77 900 650 231 936 15.84 19.79 ? 3.95 900 625 240 900 12.48 16.67 ? 4.19 999 625 240 999 21.15 16.67 4.49 891 625 240 891 11.59 16.67 ? 5.07 1008 625 240 1008 21.86 16.67 5.19 882 625 240 882 10.69 16.67 ? 5.97 873 625 240 873 9.77 16.67 ? 6.89
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-13 table a-9. overscan values, 800x600 ntsc (1 of 5) controller pixels encoder pixels overscan (percent) hblank and character clock resolution total active total h v v h h v delta hblank resol 800 777 203 1184 18.45 16.46 1.98 0.00 1 800 819 193 1248 22.63 20.58 2.05 0.00 1 800 798 198 1216 20.59 18.52 2.07 0.00 1 800 756 209 1152 16.18 13.99 2.19 0.00 1 800 714 221 1088 11.25 9.05 2.20 0.00 1 800 735 215 1120 13.79 11.52 2.26 0.00 1 805 825 191 1265 23.67 21.40 2.27 0.13 1 805 780 202 1196 19.26 16.87 2.39 0.13 1 805 750 210 1150 16.03 13.58 2.45 0.14 1 805 765 206 1173 17.68 15.23 2.45 0.14 1 805 810 195 1242 22.25 19.75 2.50 0.13 1 805 720 219 1104 12.54 9.88 2.66 0.14 1 805 795 199 1219 20.79 18.11 2.68 0.13 1 805 735 215 1127 14.32 11.52 2.80 0.14 1 810 805 196 1242 22.25 19.34 2.91 0.26 1 810 770 205 1188 18.72 15.64 3.08 0.27 1 812 750 210 1160 16.76 13.58 3.18 0.33 1 810 735 215 1134 14.85 11.52 3.33 0.28 1 819 800 197 1248 22.63 18.93 3.70 0.48 1 815 735 215 1141 15.37 11.52 3.85 0.42 1 819 750 210 1170 17.47 13.58 3.89 0.52 1 819 775 204 1209 20.13 16.05 4.08 0.50 1 825 805 196 1265 23.67 19.34 4.33 0.63 1 819 725 218 1131 14.62 10.29 4.34 0.53 1 825 784 201 1232 21.62 17.28 4.34 0.64 1 820 735 215 1148 15.89 11.52 4.37 0.55 1 825 777 203 1221 20.92 16.46 4.46 0.65 1 825 798 198 1254 23.00 18.52 4.48 0.63 1 825 770 205 1210 20.20 15.64 4.56 0.66 1 826 750 210 1180 18.17 13.58 4.59 0.70 1 825 791 200 1243 22.32 17.70 4.62 0.64 1 825 763 207 1199 19.47 14.81 4.65 0.66 1
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-14 conexant 100123b 825 756 209 1188 18.72 13.99 4.73 0.67 1 825 749 211 1177 17.96 13.17 4.79 0.67 1 825 742 213 1166 17.19 12.35 4.84 0.68 1 825 735 215 1155 16.40 11.52 4.88 0.69 1 825 714 221 1122 13.94 9.05 4.89 0.71 1 825 728 217 1144 15.59 10.70 4.89 0.69 1 825 721 219 1133 14.77 9.88 4.90 0.70 1 833 750 210 1190 18.86 13.58 5.28 0.88 1 830 735 215 1162 16.90 11.52 5.38 0.82 1 840 780 202 1248 22.63 16.87 5.76 1.02 1 840 785 201 1256 23.12 17.28 5.84 1.01 1 835 735 215 1169 17.40 11.52 5.88 0.95 1 840 765 206 1224 21.11 15.23 5.88 1.04 1 840 790 200 1264 23.61 17.70 5.91 1.01 1 840 750 210 1200 19.53 13.58 5.95 1.06 1 840 770 205 1232 21.62 15.64 5.99 1.03 1 840 755 209 1208 20.07 13.99 6.07 1.05 1 840 775 204 1240 22.13 16.05 6.08 1.03 1 840 740 213 1184 18.45 12.35 6.10 1.07 1 840 760 208 1216 20.59 14.40 6.19 1.05 1 840 730 216 1168 17.33 11.11 6.22 1.09 1 840 745 212 1192 18.99 12.76 6.24 1.07 1 840 720 219 1152 16.18 9.88 6.30 1.10 1 840 735 215 1176 17.89 11.52 6.37 1.08 1 840 725 218 1160 16.76 10.29 6.47 1.10 1 840 715 221 1144 15.59 9.05 6.54 1.11 1 847 750 210 1210 20.20 13.58 6.62 1.23 1 850 777 203 1258 23.24 16.46 6.78 1.26 1 845 735 215 1183 18.38 11.52 6.85 1.21 1 850 756 209 1224 21.11 13.99 7.12 1.30 1 854 750 210 1220 20.85 13.58 7.27 1.41 1 850 735 215 1190 18.86 11.52 7.33 1.34 1 table a-9. overscan values, 800x600 ntsc (2 of 5) controller pixels encoder pixels overscan (percent) hblank and character clock resolution total active total h v v h h v delta hblank resol
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-15 855 770 205 1254 23.00 15.64 7.36 1.39 1 850 714 221 1156 16.47 9.05 7.42 1.37 1 855 735 215 1197 19.33 11.52 7.81 1.46 1 861 750 210 1230 21.50 13.58 7.92 1.58 1 861 775 204 1271 24.03 16.05 7.98 1.53 1 860 735 215 1204 19.80 11.52 8.28 1.58 1 861 725 218 1189 18.79 10.29 8.50 1.63 1 868 750 210 1240 22.13 13.58 8.55 1.74 1 865 735 215 1211 20.26 11.52 8.74 1.71 1 875 762 207 1270 23.97 14.81 9.15 1.88 1 875 750 210 1250 22.75 13.58 9.17 1.91 1 870 735 215 1218 20.72 11.52 9.20 1.83 1 875 759 208 1265 23.67 14.40 9.26 1.88 1 875 747 211 1245 22.44 13.17 9.27 1.91 1 875 744 212 1240 22.13 12.76 9.37 1.92 1 875 756 209 1260 23.36 13.99 9.37 1.89 1 875 741 213 1235 21.81 12.35 9.47 1.93 1 875 753 210 1255 23.06 13.58 9.48 1.90 1 875 726 217 1210 20.20 10.70 9.50 1.97 1 875 738 214 1230 21.50 11.93 9.56 1.94 1 875 723 218 1205 19.87 10.29 9.58 1.98 1 875 735 215 1225 21.18 11.52 9.65 1.95 1 875 720 219 1200 19.53 9.88 9.66 1.99 1 875 717 220 1195 19.20 9.47 9.73 1.99 1 875 732 216 1220 20.85 11.11 9.74 1.95 1 882 750 210 1260 23.36 13.58 9.78 2.07 1 875 714 221 1190 18.86 9.05 9.80 2.00 1 875 729 217 1215 20.53 10.70 9.83 1.96 1 880 735 215 1232 21.62 11.52 10.10 2.06 1 889 750 210 1270 23.97 13.58 10.39 2.23 1 882 725 218 1218 20.72 10.29 10.43 2.14 1 885 735 215 1239 22.07 11.52 10.54 2.18 1 table a-9. overscan values, 800x600 ntsc (3 of 5) controller pixels encoder pixels overscan (percent) hblank and character clock resolution total active total h v v h h v delta hblank resol
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-16 conexant 100123b 890 735 215 1246 22.50 11.52 10.98 2.30 1 895 735 215 1253 22.94 11.52 11.41 2.41 1 900 735 215 1260 23.36 11.52 11.84 2.52 1 900 728 217 1248 22.63 10.70 11.93 2.55 1 900 721 219 1236 21.88 9.88 12.00 2.57 1 900 714 221 1224 21.11 9.05 12.06 2.60 1 905 735 215 1267 23.79 11.52 12.27 2.63 1 903 725 218 1247 22.57 10.29 12.28 2.62 1 910 720 219 1248 22.63 9.88 12.75 2.80 1 925 714 221 1258 23.24 9.05 14.19 3.16 1 800 777 203 1184 18.45 16.46 1.98 0.00 8 800 819 193 1248 22.63 20.58 2.05 0.00 8 800 798 198 1216 20.59 18.52 2.07 0.00 8 800 756 209 1152 16.18 13.99 2.19 0.00 8 800 714 221 1088 11.25 9.05 2.20 0.00 8 800 735 215 1120 13.79 11.52 2.26 0.00 8 840 780 202 1248 22.63 16.87 5.76 1.02 8 840 785 201 1256 23.12 17.28 5.84 1.01 8 840 765 206 1224 21.11 15.23 5.88 1.04 8 840 790 200 1264 23.61 17.70 5.91 1.01 8 840 750 210 1200 19.53 13.58 5.95 1.06 8 840 770 205 1232 21.62 15.64 5.99 1.03 8 840 755 209 1208 20.07 13.99 6.07 1.05 8 840 775 204 1240 22.13 16.05 6.08 1.03 8 840 740 213 1184 18.45 12.35 6.10 1.07 8 840 760 208 1216 20.59 14.40 6.19 1.05 8 840 730 216 1168 17.33 11.11 6.22 1.09 8 840 745 212 1192 18.99 12.76 6.24 1.07 8 840 720 219 1152 16.18 9.88 6.30 1.10 8 840 735 215 1176 17.89 11.52 6.37 1.08 8 840 725 218 1160 16.76 10.29 6.47 1.10 8 840 715 221 1144 15.59 9.05 6.54 1.11 8 table a-9. overscan values, 800x600 ntsc (4 of 5) controller pixels encoder pixels overscan (percent) hblank and character clock resolution total active total h v v h h v delta hblank resol
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-17 880 735 215 1232 21.62 11.52 10.10 2.06 8 810 805 196 1242 22.25 19.34 2.91 0.26 9 810 770 205 1188 18.72 15.64 3.08 0.27 9 810 735 215 1134 14.85 11.52 3.33 0.28 9 819 800 197 1248 22.63 18.93 3.70 0.48 9 819 750 210 1170 17.47 13.58 3.89 0.52 9 819 775 204 1209 20.13 16.05 4.08 0.50 9 819 725 218 1131 14.62 10.29 4.34 0.53 9 855 770 205 1254 23.00 15.64 7.36 1.39 9 855 735 215 1197 19.33 11.52 7.81 1.46 9 882 750 210 1260 23.36 13.58 9.78 2.07 9 882 725 218 1218 20.72 10.29 10.43 2.14 9 900 735 215 1260 23.36 11.52 11.84 2.52 9 900 728 217 1248 22.63 10.70 11.93 2.55 9 900 721 219 1236 21.88 9.88 12.00 2.57 9 900 714 221 1224 21.11 9.05 12.06 2.60 9 table a-9. overscan values, 800x600 ntsc (5 of 5) controller pixels encoder pixels overscan (percent) hblank and character clock resolution total active total h v v h h v delta hblank resol table a-10. overscan values, 800x600, pal, > 2.5 s hblank (1 of 3) controller pixels encoder pixels overscan (percent) character clock total active total h v v h h v delta resol 945 750 250 1134 13.17 13.19 ? 0.02 1 950 750 250 1140 13.63 13.19 0.44 1 950 775 242 1178 16.42 15.97 0.44 1 940 750 250 1128 12.71 13.19 ? 0.48 1 950 725 259 1102 10.65 10.07 0.58 1 950 800 235 1216 19.03 18.40 0.63 1 950 825 228 1254 21.48 20.83 0.65 1 955 750 250 1146 14.08 13.19 0.89 1 935 750 250 1122 12.24 13.19 ? 0.95 1 960 750 250 1152 14.53 13.19 1.34 1 930 750 250 1116 11.77 13.19 ? 1.42 1
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-18 conexant 100123b 925 825 228 1221 19.36 20.83 ? 1.47 1 925 800 235 1184 16.84 18.40 ? 1.56 1 965 750 250 1158 14.97 13.19 1.78 1 925 775 242 1147 14.16 15.97 ? 1.81 1 925 750 250 1110 11.30 13.19 ? 1.90 1 970 750 250 1164 15.41 13.19 2.22 1 920 750 250 1104 10.81 13.19 ? 2.38 1 975 775 242 1209 18.56 15.97 2.59 1 975 750 250 1170 15.84 13.19 2.65 1 975 800 235 1248 21.10 18.40 2.70 1 915 750 250 1098 10.33 13.19 ? 2.87 1 975 725 259 1131 12.94 10.07 2.87 1 980 750 250 1176 16.27 13.19 3.08 1 910 750 250 1092 9.83 13.19 ? 3.36 1 985 750 250 1182 16.70 13.19 3.50 1 900 825 228 1188 17.12 20.83 ? 3.71 1 905 750 250 1086 9.34 13.19 ? 3.86 1 900 800 235 1152 14.53 18.40 ? 3.87 1 990 750 250 1188 17.12 13.19 3.93 1 900 775 242 1116 11.77 15.97 ? 4.20 1 995 750 250 1194 17.54 13.19 4.34 1 1000 785 239 1256 21.61 17.01 4.59 1 1000 775 242 1240 20.60 15.97 4.62 1 1000 750 250 1200 17.95 13.19 4.75 1 1000 780 241 1248 21.10 16.32 4.79 1 1000 760 247 1216 19.03 14.24 4.79 1 1000 770 244 1232 20.08 15.28 4.80 1 1000 745 252 1192 17.40 12.50 4.90 1 1000 730 257 1168 15.70 10.76 4.94 1 1000 755 249 1208 18.49 13.54 4.95 1 1000 765 246 1224 19.56 14.58 4.97 1 960 750 250 1152 14.53 13.19 1.34 8 table a-10. overscan values, 800x600, pal, > 2.5 s hblank (2 of 3) controller pixels encoder pixels overscan (percent) character clock total active total h v v h h v delta resol
BT868/bt869 appendix a . scaling and i/o timing register calculations flicker-free video encoder with ultrascale tm technology 100123b conexant a-19 920 750 250 1104 10.81 13.19 ? 2.38 8 1000 785 239 1256 21.61 17.01 4.59 8 1000 775 242 1240 20.60 15.97 4.62 8 1000 750 250 1200 17.95 13.19 4.75 8 1000 780 241 1248 21.10 16.32 4.79 8 1000 760 247 1216 19.03 14.24 4.79 8 1000 770 244 1232 20.08 15.28 4.80 8 1000 745 252 1192 17.40 12.50 4.90 8 1000 730 257 1168 15.70 10.76 4.94 8 1000 755 249 1208 18.49 13.54 4.95 8 1000 765 246 1224 19.56 14.58 4.97 8 1000 740 254 1184 16.84 11.81 5.03 8 1000 725 259 1160 15.12 10.07 5.05 8 1000 720 261 1152 14.53 9.38 5.15 8 1000 735 256 1176 16.27 11.11 5.16 8 1000 715 263 1144 13.93 8.68 5.25 8 1040 750 250 1248 21.10 13.19 7.91 8 945 750 250 1134 13.17 13.19 ? 0.02 9 900 825 228 1188 17.12 20.83 ? 3.71 9 900 800 235 1152 14.53 18.40 ? 3.87 9 990 750 250 1188 17.12 13.19 3.93 9 900 775 242 1116 11.77 15.97 ? 4.20 9 1035 750 250 1242 20.72 13.19 7.53 9 table a-10. overscan values, 800x600, pal, > 2.5 s hblank (3 of 3) controller pixels encoder pixels overscan (percent) character clock total active total h v v h h v delta resol
appendix a . scaling and i/o timing register calculations BT868/bt869 flicker-free video encoder with ultrascale tm technology a-20 conexant 100123b
100123b conexant b-1 b appendix b. approved crystal vendors conexant conducted a series of internal tests and used the results to generate this list of approved crystal vendors. contact your local conexant field applications engineer for additional details. standard crystal (el monte, ca) phone number: (626)443-2121 fax number: (626)443-9049 e-mail: stdxtl@worldnet.att.net part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: aak13m500000gxe20a half-height/50 ppm: aal13m500000gxe20a full height/25 ppm: did not qualify mmd components (irvine, ca) phone number: (949)753-5888 fax number: (949)753-5889 e-mail: mmdcomp@earthlink.net part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50ppm total tolerance: a20ba1-13.500 mhz. half-height/50 ppm: b20ba1-13,500 mhz full height/25 ppm: did not qualify general electronics (san marcos, ca) phone number: (760)591-4170 fax number: (760)591-4164 e-mail: gedlm@4dcomm.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: pkhc49/u-13.500-.020-.005 half-height/50 ppm: pkhc49/us-13.500-.020-.005 full height/25 ppm: pkhc49/u-13.500-.0025-15r fox electronics (fort myers, fl) phone number: (941)693-0099 fax number: (941)693-1554 e-mail: barbc@foxonline.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: hc49u-13.500 mhz-/50/0/70/20 pf half height/50 ppm: hc49s 13.500-/50/0/70/20 pf full height/25 ppm: hc49u 13.500-/25/0/70/20 pf
appendix b . approved crystal vendors BT868/bt869 flicker-free video encoder with ultrascale tm technology b-2 conexant 100123b bomar (middlesex, nj) phone number: (732)356-7787 fax number: (732)356-7362 e-mail: sales@bomarcrystal.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: brc1c14f-13.50000 half height/50 ppm: acr-49s012025-13.50000 full height/25 ppm: brcie14f-13.50000 hy-q (erlanger, kentucky) phone number: (606)283-5000 fax number: (606)283-0883 e-mail: cpainter@hyqusa.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: ht81818/01 half height/50 ppm: sc30002/01 full height/25 ppm: ht81819/01 ilsi america (kirkland, wa) phone number: (425)828-4886 / (888)355-4574 fax number: (425)828-4878 e-mail: ilsiam@ilsiamerica.co part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: hc49u-25/25-13.500-20 half height/50 ppm: hc49us-fb1f20-13.500 full height/25 ppm: did not qualify cardinal components (wayne, nj) phone number: (973)785-1333 fax number: (973)785-0053 e-mail: dbabcock@cardinalxtal.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: c49-a4brc7-25-13.5d20 half height/50 ppm: clp-a4b6c4-50-13.5d20 full height/25 ppm: c49-a4b6c4-25-13.5d20 raltron electronics corp. (miami, fl) phone number: (305)593-6033 fax number: (305)594-3973 e-mail: maria@raltron.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: a-13.500-20-rs1 half height/50 ppm: as-13.500-20-rs1 full height/25 ppm: a-13.500-20-rs1 valpey-fisher (hopkinton, ma) phone number: (800)982-5737 fax number: (508)497-6377
BT868/bt869 appendix b . approved crystal vendors flicker-free video encoder with ultrascale tm technology 100123b conexant b-3 e-mail: angleassoc@aol.com part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: m490013.500020rsvm half height/50 ppm: m49k013.50002099vm full height/25 ppm: m490013.50002099vm telequarz group (germany) phone number: telequarz-usa inc. (ft. mill, sc): (803)547-0770 fax number: (507)547-0775 e-mail: info@telequarz.de part numbers for 13.500 mhz, fundamental, 20pf load crystal with an hc49u type of package: full height/50 ppm total tolerance: tq rsd 13.5fh50 half height/50 ppm: tqrsd 13.5lp50 full height/25 ppm: tq rsd 13.5fh25
appendix b . approved crystal vendors BT868/bt869 flicker-free video encoder with ultrascale tm technology b-4 conexant 100123b

further information literature@conexant.com (800) 854-8099 (north america) (949) 483-6996 (international) printed in usa world headquarters conexant systems, inc. 4311 jamboree road newport beach, ca 92660-3007 phone: (949) 483-4600 fax 1: (949) 483-4078 fax 2: (949) 483-4391 americas u.s. northwest/ pacific northwest ? santa clara phone: (408) 249-9696 fax: (408) 249-7113 u.s. southwest ? los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. southwest ? orange county phone: (949) 483-9119 fax: (949) 483-9090 u.s. southwest ? san diego phone: (858) 713-3374 fax: (858) 713-4001 u.s. north central ? illinois phone: (630) 773-3454 fax: (630) 773-3907 u.s. south central ? texas phone: (972) 733-0723 fax: (972) 407-0639 u.s. northeast ? massachusetts phone: (978) 367-3200 fax: (978) 256-6868 u.s. southeast ? north carolina phone: (919) 858-9110 fax: (919) 858-8669 u.s. southeast ? florida/ south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. mid-atlantic ? pennsylvania phone: (215) 244-6784 fax: (215) 244-9292 canada ? ontario phone: (613) 271-2358 fax: (613) 271-2359 europe europe central ? germany phone: +49 89 829-1320 fax: +49 89 834-2734 europe north ? england phone: +44 1344 486444 fax: +44 1344 486555 europe ? israel/greece phone: +972 9 9524000 fax: +972 9 9573732 europe south ? france phone: +33 1 41 44 36 51 fax: +33 1 41 44 36 90 europe mediterranean ? italy phone: +39 02 93179911 fax: +39 02 93179913 europe ? sweden phone: +46 (0) 8 5091 4319 fax: +46 (0) 8 590 041 10 europe ? finland phone: +358 (0) 9 85 666 435 fax: +358 (0) 9 85 666 220 asia ? pacific taiwan phone: (886-2) 2-720-0282 fax: (886-2) 2-757-6760 australia phone: (61-2) 9869 4088 fax: (61-2) 9869 4077 china ? central phone: 86-21-6361-2515 fax: 86-21-6361-2516 china ? south phone: (852) 2 827-0181 fax: (852) 2 827-6488 china ? south (satellite) phone: (86) 755-518-2495 china ? north phone: (86-10) 8529-9777 fax: (86-10) 8529-9778 india phone: (91-11) 692-4789 fax: (91-11) 692-4712 korea phone: (82-2) 565-2880 fax: (82-2) 565-1440 korea (satellite) phone: (82-53) 745-2880 fax: (82-53) 745-1440 singapore phone: (65) 737 7355 fax: (65) 737 9077 japan phone: (81-3) 5371 1520 fax: (81-3) 5371 1501 www.conexant.com 0 . 0 sa l es offi ces

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